From feddd37297d2157504540aa861e86e7e2aeba782 Mon Sep 17 00:00:00 2001 From: Crystal Guo Date: Wed, 20 Nov 2024 10:40:57 +0800 Subject: soc/mediatek: Rename dpm to dpm_v1 MT8196 equips new DPM hardware which is different from precedent SoCs. Therefore, we need implement a new DPM loader (said version 2) to run the blob. Considering the version iteration, rename the original dpm to dpm_v1. TEST=Build pass. BUG=b:317009620 Change-Id: I07afb8f5c23e96aad3c6cb0887cb7efd16ebf296 Signed-off-by: Crystal Guo Reviewed-on: https://review.coreboot.org/c/coreboot/+/85211 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu Reviewed-by: Yidi Lin --- src/soc/mediatek/common/include/soc/dpm.h | 56 ---------------------------- src/soc/mediatek/common/include/soc/dpm_v1.h | 56 ++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 56 deletions(-) delete mode 100644 src/soc/mediatek/common/include/soc/dpm.h create mode 100644 src/soc/mediatek/common/include/soc/dpm_v1.h (limited to 'src/soc/mediatek/common/include') diff --git a/src/soc/mediatek/common/include/soc/dpm.h b/src/soc/mediatek/common/include/soc/dpm.h deleted file mode 100644 index e72b6a1f3d..0000000000 --- a/src/soc/mediatek/common/include/soc/dpm.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SOC_MEDIATEK_COMMON_DPM_H__ -#define __SOC_MEDIATEK_COMMON_DPM_H__ - -#include -#include -#include - -struct dpm_regs { - u32 sw_rstn; - u32 rsvd_0[3072]; - u32 mclk_div; - u32 rsvd_1[3071]; - u32 twam_window_len; - u32 twam_mon_type; - u32 rsvd_2[1022]; - u32 low_power_cfg_0; - u32 low_power_cfg_1; - u32 rsvd_3[1]; - u32 fsm_out_ctrl_0; - u32 rsvd_4[8]; - u32 fsm_cfg_1; - u32 low_power_cfg_3; - u32 dfd_dbug_0; - u32 rsvd_5[28]; - u32 status_4; -}; - -check_member(dpm_regs, mclk_div, 0x3004); -check_member(dpm_regs, twam_window_len, 0x6004); -check_member(dpm_regs, low_power_cfg_0, 0x7004); -check_member(dpm_regs, low_power_cfg_1, 0x7008); -check_member(dpm_regs, fsm_out_ctrl_0, 0x7010); -check_member(dpm_regs, fsm_cfg_1, 0x7034); -check_member(dpm_regs, low_power_cfg_3, 0x7038); -check_member(dpm_regs, dfd_dbug_0, 0x703C); -check_member(dpm_regs, status_4, 0x70B0); - -#define DPM_SW_RSTN_RESET BIT(0) -#define DPM_MEM_RATIO_OFFSET 28 -#define DPM_MEM_RATIO_MASK (0x3 << DPM_MEM_RATIO_OFFSET) -#define DPM_MEM_RATIO_CFG1 (1 << DPM_MEM_RATIO_OFFSET) -#define DRAMC_MCU_SRAM_ISOINT_B_LSB BIT(1) -#define DRAMC_MCU2_SRAM_ISOINT_B_LSB BIT(1) -#define DRAMC_MCU_SRAM_SLEEP_B_LSB BIT(4) -#define DRAMC_MCU2_SRAM_SLEEP_B_LSB BIT(4) - -static struct dpm_regs *const mtk_dpm = (void *)DPM_CFG_BASE; - -void dpm_reset(struct mtk_mcu *mcu); -int dpm_init(void); -int dpm_4ch_para_setting(void); -int dpm_4ch_init(void); - -#endif /* __SOC_MEDIATEK_COMMON_DPM_H__ */ diff --git a/src/soc/mediatek/common/include/soc/dpm_v1.h b/src/soc/mediatek/common/include/soc/dpm_v1.h new file mode 100644 index 0000000000..65623a2671 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dpm_v1.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_COMMON_DPM_V1_H__ +#define __SOC_MEDIATEK_COMMON_DPM_V1_H__ + +#include +#include +#include + +struct dpm_regs { + u32 sw_rstn; + u32 rsvd_0[3072]; + u32 mclk_div; + u32 rsvd_1[3071]; + u32 twam_window_len; + u32 twam_mon_type; + u32 rsvd_2[1022]; + u32 low_power_cfg_0; + u32 low_power_cfg_1; + u32 rsvd_3[1]; + u32 fsm_out_ctrl_0; + u32 rsvd_4[8]; + u32 fsm_cfg_1; + u32 low_power_cfg_3; + u32 dfd_dbug_0; + u32 rsvd_5[28]; + u32 status_4; +}; + +check_member(dpm_regs, mclk_div, 0x3004); +check_member(dpm_regs, twam_window_len, 0x6004); +check_member(dpm_regs, low_power_cfg_0, 0x7004); +check_member(dpm_regs, low_power_cfg_1, 0x7008); +check_member(dpm_regs, fsm_out_ctrl_0, 0x7010); +check_member(dpm_regs, fsm_cfg_1, 0x7034); +check_member(dpm_regs, low_power_cfg_3, 0x7038); +check_member(dpm_regs, dfd_dbug_0, 0x703C); +check_member(dpm_regs, status_4, 0x70B0); + +#define DPM_SW_RSTN_RESET BIT(0) +#define DPM_MEM_RATIO_OFFSET 28 +#define DPM_MEM_RATIO_MASK (0x3 << DPM_MEM_RATIO_OFFSET) +#define DPM_MEM_RATIO_CFG1 (1 << DPM_MEM_RATIO_OFFSET) +#define DRAMC_MCU_SRAM_ISOINT_B_LSB BIT(1) +#define DRAMC_MCU2_SRAM_ISOINT_B_LSB BIT(1) +#define DRAMC_MCU_SRAM_SLEEP_B_LSB BIT(4) +#define DRAMC_MCU2_SRAM_SLEEP_B_LSB BIT(4) + +static struct dpm_regs *const mtk_dpm = (void *)DPM_CFG_BASE; + +void dpm_reset(struct mtk_mcu *mcu); +int dpm_init(void); +int dpm_4ch_para_setting(void); +int dpm_4ch_init(void); + +#endif /* __SOC_MEDIATEK_COMMON_DPM_V1_H__ */ -- cgit v1.2.3