From d41a5ae4890f40da060bfd73fda344b4c5edab93 Mon Sep 17 00:00:00 2001 From: Ryan Chuang Date: Fri, 18 Jun 2021 19:47:39 +0800 Subject: soc/mediatek/common: Add DPM_FOUR_CHANNEL option Add DPM_FOUR_CHANNEL option for 4 channel configuration for DPM. Publicize reset_dpm() as dpm_reset() for external reference. Signed-off-by: Ryan Chuang Change-Id: If6e0d5c4d16a7ddd69c4a427488f8899870db327 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55719 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/common/include/soc/dpm.h | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'src/soc/mediatek/common/include') diff --git a/src/soc/mediatek/common/include/soc/dpm.h b/src/soc/mediatek/common/include/soc/dpm.h index 7262e09a6f..8c110aaaf1 100644 --- a/src/soc/mediatek/common/include/soc/dpm.h +++ b/src/soc/mediatek/common/include/soc/dpm.h @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_MEDIATEK_DPM_H__ -#define __SOC_MEDIATEK_DPM_H__ +#ifndef __SOC_MEDIATEK_COMMON_DPM_H__ +#define __SOC_MEDIATEK_COMMON_DPM_H__ #include +#include #include #include @@ -41,9 +42,16 @@ check_member(dpm_regs, status_4, 0x70B0); #define DPM_MEM_RATIO_OFFSET 28 #define DPM_MEM_RATIO_MASK (0x3 << DPM_MEM_RATIO_OFFSET) #define DPM_MEM_RATIO_CFG1 (1 << DPM_MEM_RATIO_OFFSET) +#define DRAMC_MCU_SRAM_ISOINT_B_LSB BIT(1) +#define DRAMC_MCU2_SRAM_ISOINT_B_LSB BIT(1) +#define DRAMC_MCU_SRAM_SLEEP_B_LSB BIT(4) +#define DRAMC_MCU2_SRAM_SLEEP_B_LSB BIT(4) static struct dpm_regs *const mtk_dpm = (void *)DPM_CFG_BASE; +void dpm_reset(struct mtk_mcu *mcu); int dpm_init(void); +int dpm_4ch_para_setting(void); +int dpm_4ch_init(void); -#endif /* __SOC_MEDIATEK_MT8192_DPM_H__ */ +#endif /* __SOC_MEDIATEK_COMMON_DPM_H__ */ -- cgit v1.2.3