From cd83bf8874b13639bbd0b9e3b1270a5771d5e5bc Mon Sep 17 00:00:00 2001 From: Qii Wang Date: Fri, 20 Nov 2020 17:36:07 +0800 Subject: soc/mediatek/mt8192: add i2c driver support Add I2C controller for MT8192, and revise the common I2C driver to support I2C controller running in APDMA async mode. In that case we have to initiate a different handshake protocol and reset I2C differently. BUG=b:155715435 TEST=Asurada boots up to shell Signed-off-by: Qii Wang Change-Id: I13835e00eb674a93aa5496a9870d1e601e263368 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47800 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/mediatek/common/include/soc/i2c_common.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'src/soc/mediatek/common/include') diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h index 0100e261cd..d2da27ef4c 100644 --- a/src/soc/mediatek/common/include/soc/i2c_common.h +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -38,6 +38,12 @@ enum { I2C_DMA_INT_FLAG_NONE = 0x0, I2C_DMA_CLR_FLAG = 0x0, I2C_DMA_FLUSH_FLAG = 0x1, + I2C_DMA_ASYNC_MODE = 0x0004, + I2C_DMA_SKIP_CONFIG = 0x0010, + I2C_DMA_DIR_CHANGE = 0x0200, + I2C_DMA_WARM_RST = 0x1, + I2C_DMA_HARD_RST = 0x2, + I2C_DMA_HANDSHAKE_RST = 0x4, }; enum { @@ -46,6 +52,11 @@ enum { I2C_CONTROL_MASK = (0x3f << 1) }; +enum { + I2C_APDMA_NOASYNC = 0, + I2C_APDMA_ASYNC = 1, +}; + /* Register mask */ enum { I2C_HS_NACKERR = (1 << 2), @@ -53,6 +64,13 @@ enum { I2C_TRANSAC_COMP = (1 << 0), }; +/* reset bits */ +enum { + I2C_CLR_FLAG = 0x0, + I2C_SOFT_RST = 0x1, + I2C_HANDSHAKE_RST = 0x20, +}; + /* i2c control bits */ enum { ASYNC_MODE = (1 << 9), @@ -80,6 +98,7 @@ enum { struct mtk_i2c { struct mt_i2c_regs *i2c_regs; struct mt_i2c_dma_regs *i2c_dma_regs; + uint32_t mt_i2c_flag; }; extern struct mtk_i2c mtk_i2c_bus_controller[]; -- cgit v1.2.3