From 435ee357e9c4e09032e4919b4b815fce1fc7d555 Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Tue, 1 Jun 2021 11:42:27 +0800 Subject: soc/mediatek/mt8195: add power and power control for eDP 1. Add API of TVD_PLL1 mt_pll_set_tvd_pll1_freq() for setting rate. 2. Add API of TVD_PLL1 edp_mux_set_sel() for mux sel. 3. Add eDP power domain control. BUG=b:189985956 Signed-off-by: Jitao Shi Change-Id: I9e43e0ffeb7b8bcd1786a8d2f5acbf22d5ab501f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55346 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/common/include/soc/pll_common.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/mediatek/common/include') diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index cb22796ebf..2ebb71aa2e 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -70,6 +70,8 @@ int pll_set_rate(const struct pll *pll, u32 rate); void mt_pll_init(void); void mt_pll_raise_little_cpu_freq(u32 freq); void mt_pll_raise_cci_freq(u32 freq); +void mt_pll_set_tvd_pll1_freq(u32 freq); +void edp_mux_set_sel(u32 sel); enum fmeter_type { FMETER_ABIST = 0, -- cgit v1.2.3