From 3b217d5c69de950fde7a15e0c3c109b40f64a9c4 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Wed, 7 Aug 2019 10:15:48 +0800 Subject: soc/mediatek: dsi: Refactor video timing calculation The video timing should be based on PHY timing. Some values can be ignored on 8173 because of fixed values in PHY but should be calculated for newer platforms like 8183. BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4 Signed-off-by: Hung-Te Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/34772 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/mediatek/common/include/soc/dsi_common.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/soc/mediatek/common/include') diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index bfdd4073d6..0738876aea 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -129,7 +129,9 @@ enum { PACKED_PS_16BIT_RGB565 = (0 << 16), LOOSELY_PS_18BIT_RGB666 = (1 << 16), PACKED_PS_18BIT_RGB666 = (2 << 16), - PACKED_PS_24BIT_RGB888 = (3 << 16) + PACKED_PS_24BIT_RGB888 = (3 << 16), + + DSI_PSCON_CUSTOM_HEADER_SHIFT = 26, }; /* DSI_CMDQ_SIZE */ @@ -318,6 +320,8 @@ struct mtk_phy_timing { u8 clk_hs_prepare; u8 clk_hs_post; u8 clk_hs_exit; + + u32 d_phy; }; /* Functions that each SOC should provide. */ -- cgit v1.2.3