From 7ece24634c4c5b360b515f63861361daee8f0537 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Mon, 5 Aug 2019 03:08:57 +0800 Subject: soc/mediatek/mt8173: Refactor display driver to share common parts Move those will be shared by other MTK SOCs (for example, MT8183) to common/ddp.c. BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Oak Change-Id: Ie5709ab6e263caa21fdf7e799dc2ee884ffaf800 Signed-off-by: Yongqiang Niu Reviewed-on: https://review.coreboot.org/c/coreboot/+/34515 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/mediatek/common/ddp.c | 82 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 src/soc/mediatek/common/ddp.c (limited to 'src/soc/mediatek/common/ddp.c') diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c new file mode 100644 index 0000000000..173fa90cd7 --- /dev/null +++ b/src/soc/mediatek/common/ddp.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) +#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) + +void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color) +{ + write32(&disp_ovl[idx]->roi_size, height << 16 | width); + write32(&disp_ovl[idx]->roi_bgclr, color); +} + +void rdma_start(void) +{ + setbits_le32(&disp_rdma0->global_con, RDMA_ENGINE_EN); +} + +void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size) +{ + u32 threshold; + u32 reg; + + clrsetbits_le32(&disp_rdma0->size_con_0, 0x1FFF, width); + clrsetbits_le32(&disp_rdma0->size_con_1, 0xFFFFF, height); + + /* + * Enable FIFO underflow since DSI and DPI can't be blocked. Set the + * output threshold to 6 microseconds with 7/6 overhead to account for + * blanking, and with a pixel depth of 4 bytes: + */ + threshold = pixel_clk * 4 * 7 / 1000; + + if (threshold > fifo_size) + threshold = fifo_size; + + reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(fifo_size) | + RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); + + write32(&disp_rdma0->fifo_con, reg); +} + +void color_start(u32 width, u32 height) +{ + + write32(&disp_color0->width, width); + write32(&disp_color0->height, height); + write32(&disp_color0->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL); + write32(&disp_color0->start, BIT(0)); +} + +void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height) +{ + struct disp_ovl_regs *const ovl0 = disp_ovl[0]; + write32(&ovl0->layer[0].con, fmt << 12); + write32(&ovl0->layer[0].src_size, height << 16 | width); + write32(&ovl0->layer[0].pitch, (width * bpp) & 0xFFFF); + + /* Enable layer */ + write32(&ovl0->rdma[0].ctrl, BIT(0)); + write32(&ovl0->rdma[0].mem_gmc_setting, RDMA_MEM_GMC); + + setbits_le32(&ovl0->src_con, BIT(0)); +} -- cgit v1.2.3