From fe85ae3f41912ce021c0ffe9a0cfcf4798da5da1 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 27 Aug 2015 16:35:06 -0700 Subject: skylake: PCR: Add Port ID for SCS Add the PCR Port ID for the storage controllers and reformat to put the PCR PIDs in increasing order. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0f0144ef79d3691fa120dafc9a31d2a681bf2a28 Signed-off-by: Patrick Georgi Original-Commit-Id: 208242f58759899f17e52593ed6e1dd631334ac9 Original-Change-Id: I942bcf01b0576136c0039aa62f38fe7f3454ba8a Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/295905 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11532 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/include/soc/pcr.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h index c8a4425fcc..bf3161b9ac 100644 --- a/src/soc/intel/skylake/include/soc/pcr.h +++ b/src/soc/intel/skylake/include/soc/pcr.h @@ -78,9 +78,10 @@ #define PID_GPIOCOM2 0xAD #define PID_GPIOCOM1 0xAE #define PID_GPIOCOM0 0xAF -#define PID_LPC 0xC7 -#define PID_ITSS 0xC4 +#define PID_SCS 0xC0 #define PID_RTC 0xC3 +#define PID_ITSS 0xC4 +#define PID_LPC 0xC7 #define PID_SERIALIO 0xCB #define PID_DMI 0xEF -- cgit v1.2.3