From fd46b497ead843eccfd80124ca8fbba7e57a3631 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 8 Sep 2021 14:30:07 +0200 Subject: lynxpoint/broadwell: Correct L1 exit latency with ASPM Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does the same. Correct the condition accordingly. On Lynx Point, also remove a now-redundant write to the LCAP register (offset 0x4c). Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/57501 Reviewed-by: Lean Sheng Tan Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/pch/pcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 966a25d661..4847da6788 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -522,7 +522,7 @@ static void pch_pcie_early(struct device *dev) pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); /* Set L1 exit latency in LCAP register. */ - if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) + if ((pci_read_config8(dev, 0xf5) & 0x1) || do_aspm) pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); else pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); -- cgit v1.2.3