From f3885618d91d47be8d6ffddeb4118d7027863c64 Mon Sep 17 00:00:00 2001
From: Lijian Zhao <lijian.zhao@intel.com>
Date: Thu, 9 Nov 2017 15:01:33 -0800
Subject: soc/intel/cannonlake: Define default LPSS clock

Default LPSS clock need to be defined for SOC.

TEST=Turn on COMMON_I2C_DEBUG, add I2C clock entry and check I2C
programing properly during coreboot.

Change-Id: I2c6b9bb23950b09f6f05e3ef762ccb1a260efc5f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/cannonlake/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/soc/intel')

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 36ea922ba9..f4d524a925 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -131,6 +131,10 @@ config CPU_BCLK_MHZ
 	int
 	default 100
 
+config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
+	int
+	default 120
+
 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 	int
 	default 3
-- 
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