From f00b3375257c4128551b040f2b6a0d086c267bc9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 7 May 2020 01:32:32 +0200 Subject: soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CB:41106 revealed that mb/intel/cedarisland already sets FSP-S UPD (see CB:40735) while the required includes are still missing in CPX. Buildbot did not fail because `ramstage.c` never was (implicitly) included. Fix this problem by making SKX/CPX share a common ramstage header for now by moving the one from SKX. Test: Build cedarisland_crb Change-Id: I9cd25edd167ec71ee98c7ffa4fa6f95ca73a75e9 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/41116 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov --- src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h | 6 ------ src/soc/intel/xeon_sp/include/soc/ramstage.h | 17 +++++++++++++++++ src/soc/intel/xeon_sp/skx/include/soc/ramstage.h | 17 ----------------- 3 files changed, 17 insertions(+), 23 deletions(-) delete mode 100644 src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h create mode 100644 src/soc/intel/xeon_sp/include/soc/ramstage.h delete mode 100644 src/soc/intel/xeon_sp/skx/include/soc/ramstage.h (limited to 'src/soc/intel') diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h b/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h deleted file mode 100644 index 28e8d1a1dc..0000000000 --- a/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include - -extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/xeon_sp/include/soc/ramstage.h b/src/soc/intel/xeon_sp/include/soc/ramstage.h new file mode 100644 index 0000000000..18373f8884 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/ramstage.h @@ -0,0 +1,17 @@ +/* This file is part of the coreboot project. */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include +#include +#include +#include + +void xeon_sp_init_cpus(struct device *dev); +void mainboard_silicon_init_params(FSPS_UPD *params); + +extern struct pci_operations soc_pci_ops; + +#endif diff --git a/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h b/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h deleted file mode 100644 index 18373f8884..0000000000 --- a/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h +++ /dev/null @@ -1,17 +0,0 @@ -/* This file is part of the coreboot project. */ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _SOC_RAMSTAGE_H_ -#define _SOC_RAMSTAGE_H_ - -#include -#include -#include -#include - -void xeon_sp_init_cpus(struct device *dev); -void mainboard_silicon_init_params(FSPS_UPD *params); - -extern struct pci_operations soc_pci_ops; - -#endif -- cgit v1.2.3