From ea2a38be323173075db3b13729a4006ea1fef72d Mon Sep 17 00:00:00 2001 From: Joey Peng Date: Tue, 25 Apr 2023 15:18:00 +0800 Subject: soc/intel/alderlake: Disable C1E on RPL CPUs Since disabling C1E could improve acoustic noise for RPL, add judgement in SOC code to disable C1E on RPL CPUs and enabling it on ADL CPUs . BUG=b:278654939 TEST:emerge-brya coreboot Signed-off-by: Joey Peng Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74727 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Nick Vaccaro --- src/soc/intel/alderlake/fsp_params.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 7789cec747..d5fa51a7ab 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -1011,6 +1011,11 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, s_cfg->PkgCStateDemotion = 0; else s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion; + + if (cpu_id == CPUID_RAPTORLAKE_P_J0 || cpu_id == CPUID_RAPTORLAKE_P_Q0) + s_cfg->C1e = 0; + else + s_cfg->C1e = 1; } static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, -- cgit v1.2.3