From da541327d2ecfc9043205a7bd81c0ed71c4313fa Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 16 May 2022 16:21:51 +0200 Subject: soc/intel/elkhartlake: Enable SMBus depending on dev state Program the `SmbusEnable` FSP UPD according to the SMBus PCI device's state in the devicetree. This avoids having to manually make sure the SMBus PCI device and the `SmbusEnable` setting are in sync. Change-Id: I275a981f914a55dc57a75e7d436912ff0255a293 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/64402 Reviewed-by: Lean Sheng Tan Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/elkhartlake/chip.h | 3 --- src/soc/intel/elkhartlake/romstage/fsp_params.c | 3 +-- 2 files changed, 1 insertion(+), 5 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 3e1d56e17e..8764657b19 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -227,9 +227,6 @@ struct soc_intel_elkhartlake_config { /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; - /* SMBus */ - uint8_t SmbusEnable; - /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; uint8_t ScsEmmcDdr50Enabled; diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index b8aaca78db..5c8c995959 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -64,8 +64,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->PchMasterClockGating = 1; m_cfg->PchMasterPowerGating = 1; - /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; + m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS); /* Set debug probe type */ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT; -- cgit v1.2.3