From d19ebe0bd5c05badc7b800eab625559a8ac7d2f0 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 12 Jul 2023 02:10:17 +0000 Subject: soc/intel: Rename pcr.asl to pch_pcr.asl The PCR (Private Configuration Register) is applicable to access the P2SB register space starting with the Intel SkyLake generation of SoC. Prior to Intel Meteor Lake SoC generation, the only P2SB existed inside the PCH die. Starting with Meteor Lake SoC, there are two P2SB, one in SoC die (same as PCH die for U/H SoC) and another in IOE die. This patch renames pcr.asl to pch_pcr.asl to reflect the actual source of the P2SB IP in the die (i.e., SoC die or PCH die). BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: Idb66293eaab01e1d4bcd4e9482157575fb0adf04 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/76407 Reviewed-by: Sridhar Siricilla Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal --- src/soc/intel/alderlake/acpi/southbridge.asl | 2 +- src/soc/intel/cannonlake/acpi/southbridge.asl | 2 +- src/soc/intel/common/acpi/pch_pcr.asl | 75 ++++++++++++++++++++++++++ src/soc/intel/common/acpi/pcr.asl | 75 -------------------------- src/soc/intel/elkhartlake/acpi/southbridge.asl | 2 +- src/soc/intel/jasperlake/acpi/southbridge.asl | 2 +- src/soc/intel/meteorlake/acpi/southbridge.asl | 2 +- src/soc/intel/skylake/acpi/pch.asl | 2 +- src/soc/intel/tigerlake/acpi/southbridge.asl | 2 +- src/soc/intel/xeon_sp/acpi/gpio.asl | 2 +- 10 files changed, 83 insertions(+), 83 deletions(-) create mode 100644 src/soc/intel/common/acpi/pch_pcr.asl delete mode 100644 src/soc/intel/common/acpi/pcr.asl (limited to 'src/soc/intel') diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index e663adc3c7..d14dd66990 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -6,7 +6,7 @@ #include /* PCR access */ -#include +#include /* PCH clock */ #include "camera_clock_ctl.asl" diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 052847d08c..20d4bfd897 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* PCR access */ -#include +#include /* eMMC, SD Card */ #include "scs.asl" diff --git a/src/soc/intel/common/acpi/pch_pcr.asl b/src/soc/intel/common/acpi/pch_pcr.asl new file mode 100644 index 0000000000..2a940a3160 --- /dev/null +++ b/src/soc/intel/common/acpi/pch_pcr.asl @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* + * Calculate PCR register base at specified PID + * Arg0 - PCR Port ID + */ +Method (PCRB, 1, NotSerialized) +{ + Return (CONFIG_PCR_BASE_ADDRESS + (Arg0 << PCR_PORTID_SHIFT)) +} + +/* + * Read a PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + */ +Method (PCRR, 2, Serialized) +{ + OperationRegion (PCRD, SystemMemory, PCRB (Arg0) + Arg1, 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + Return (DATA) +} + +/* + * AND a value with PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + * Arg2 - Value to AND + */ +Method (PCRA, 3, Serialized) +{ + OperationRegion (PCRD, SystemMemory, PCRB (Arg0) + Arg1, 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + DATA &= Arg2 + + /* + * After every write one needs to read an innocuous register + * to ensure the writes are completed for certain ports. This is done + * for all ports so that the callers don't need the per-port knowledge + * for each transaction. + */ + PCRR (Arg0, Arg1) +} + +/* + * OR a value with PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + * Arg2 - Value to OR + */ +Method (PCRO, 3, Serialized) +{ + OperationRegion (PCRD, SystemMemory, PCRB (Arg0) + Arg1, 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + DATA |= Arg2 + + /* + * After every write one needs to read an innocuous register + * to ensure the writes are completed for certain ports. This is done + * for all ports so that the callers don't need the per-port knowledge + * for each transaction. + */ + PCRR (Arg0, Arg1) +} diff --git a/src/soc/intel/common/acpi/pcr.asl b/src/soc/intel/common/acpi/pcr.asl deleted file mode 100644 index 2a940a3160..0000000000 --- a/src/soc/intel/common/acpi/pcr.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -/* - * Calculate PCR register base at specified PID - * Arg0 - PCR Port ID - */ -Method (PCRB, 1, NotSerialized) -{ - Return (CONFIG_PCR_BASE_ADDRESS + (Arg0 << PCR_PORTID_SHIFT)) -} - -/* - * Read a PCR register at specified PID and offset - * Arg0 - PCR Port ID - * Arg1 - Register Offset - */ -Method (PCRR, 2, Serialized) -{ - OperationRegion (PCRD, SystemMemory, PCRB (Arg0) + Arg1, 4) - Field (PCRD, DWordAcc, NoLock, Preserve) - { - DATA, 32 - } - Return (DATA) -} - -/* - * AND a value with PCR register at specified PID and offset - * Arg0 - PCR Port ID - * Arg1 - Register Offset - * Arg2 - Value to AND - */ -Method (PCRA, 3, Serialized) -{ - OperationRegion (PCRD, SystemMemory, PCRB (Arg0) + Arg1, 4) - Field (PCRD, DWordAcc, NoLock, Preserve) - { - DATA, 32 - } - DATA &= Arg2 - - /* - * After every write one needs to read an innocuous register - * to ensure the writes are completed for certain ports. This is done - * for all ports so that the callers don't need the per-port knowledge - * for each transaction. - */ - PCRR (Arg0, Arg1) -} - -/* - * OR a value with PCR register at specified PID and offset - * Arg0 - PCR Port ID - * Arg1 - Register Offset - * Arg2 - Value to OR - */ -Method (PCRO, 3, Serialized) -{ - OperationRegion (PCRD, SystemMemory, PCRB (Arg0) + Arg1, 4) - Field (PCRD, DWordAcc, NoLock, Preserve) - { - DATA, 32 - } - DATA |= Arg2 - - /* - * After every write one needs to read an innocuous register - * to ensure the writes are completed for certain ports. This is done - * for all ports so that the callers don't need the per-port knowledge - * for each transaction. - */ - PCRR (Arg0, Arg1) -} diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl index 2da44bcb79..8b0748dc62 100644 --- a/src/soc/intel/elkhartlake/acpi/southbridge.asl +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -9,7 +9,7 @@ #include "pci_irqs.asl" /* PCR access */ -#include +#include /* GPIO controller */ #include "gpio.asl" diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index 93e538edc3..a463304228 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -9,7 +9,7 @@ #include "pci_irqs.asl" /* PCR access */ -#include +#include /* PCH clock */ #include "camera_clock_ctl.asl" diff --git a/src/soc/intel/meteorlake/acpi/southbridge.asl b/src/soc/intel/meteorlake/acpi/southbridge.asl index 6ecadbbd29..2d24fb2a54 100644 --- a/src/soc/intel/meteorlake/acpi/southbridge.asl +++ b/src/soc/intel/meteorlake/acpi/southbridge.asl @@ -6,7 +6,7 @@ #include /* PCR access */ -#include +#include /* PCH clock */ #include "camera_clock_ctl.asl" diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 0aa8f95761..a2ab35c2da 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -27,7 +27,7 @@ #include "pcie.asl" /* PCR Access */ -#include +#include /* PMC 0:1f.2 */ #include "pmc.asl" diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 83453e2633..c54bc675f2 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -6,7 +6,7 @@ #include /* PCR access */ -#include +#include /* PCH clock */ #include "camera_clock_ctl.asl" diff --git a/src/soc/intel/xeon_sp/acpi/gpio.asl b/src/soc/intel/xeon_sp/acpi/gpio.asl index ea00b03ee4..a67bdd7d5a 100644 --- a/src/soc/intel/xeon_sp/acpi/gpio.asl +++ b/src/soc/intel/xeon_sp/acpi/gpio.asl @@ -4,7 +4,7 @@ #include #include #include -#include +#include Device (GPIO) { -- cgit v1.2.3