From d08057aa20d8dff404ba9121a5d2052ae6575356 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 12 Feb 2015 22:51:57 -0700 Subject: intel/fsp_baytrail: Add PCI Root Port IRQ Routing This change generates the ASL tables needed for the PCIe bridge routing. It generates this ASL (swizzled for each of the 8 functions) Name(RP1P, Package() { Package() {0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, Package() {0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, Package() {0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, Package() {0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, }) Name(RP1A, Package() { Package() {0x0000ffff, 0, 0, 20 }, Package() {0x0000ffff, 1, 0, 21 }, Package() {0x0000ffff, 2, 0, 22 }, Package() {0x0000ffff, 3, 0, 23 }, }) Device(RP01) { Name(_ADR, 0x1c0001) Name(_PRW, Package() { 0, 0 }) Method(_PRT,0) { If(PICM) { Return (RP1A) } Else { Return (RP1P) } } } Change-Id: Id51261c11f8457fe2150f2b646aafc4fe1ffec30 Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/8429 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/fsp_baytrail/acpi/irq_helper.h | 69 +++++++++++++++++++++++++++- src/soc/intel/fsp_baytrail/acpi/irqroute.asl | 7 +++ src/soc/intel/fsp_baytrail/baytrail/irq.h | 3 ++ 3 files changed, 77 insertions(+), 2 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h index a0bcbabbbc..4e64ce7f5d 100644 --- a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h +++ b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h @@ -37,24 +37,89 @@ #undef PIRQ_PIC_ROUTES #undef PIRQ_PIC #undef IRQROUTE_H +#undef ROOTPORT_METHODS +#undef RP_METHOD +#undef ROOTPORT_IRQ_ROUTES +#undef RP_IRQ_ROUTES #if defined(PIC_MODE) #define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } +#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ +Name(prefix_ ## func_ ## P, Package() \ +{ \ + ACPI_DEV_IRQ(0x0000, 0, a_), \ + ACPI_DEV_IRQ(0x0000, 1, b_), \ + ACPI_DEV_IRQ(0x0000, 2, c_), \ + ACPI_DEV_IRQ(0x0000, 3, d_), \ +}) + +/* define as blank so ROOTPORT_METHODS only gets inserted once */ +#define ROOTPORT_METHODS(prefix_, dev_) + #else /* defined(PIC_MODE) */ #define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } -#endif +#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ +Name(prefix_ ## func_ ## A, Package() \ +{ \ + ACPI_DEV_IRQ(0x0000, 0, a_), \ + ACPI_DEV_IRQ(0x0000, 1, b_), \ + ACPI_DEV_IRQ(0x0000, 2, c_), \ + ACPI_DEV_IRQ(0x0000, 3, d_), \ +}) + +#define ROOTPORT_METHODS(prefix_, dev_) \ + RP_METHOD(prefix_, dev_, 0) \ + RP_METHOD(prefix_, dev_, 1) \ + RP_METHOD(prefix_, dev_, 2) \ + RP_METHOD(prefix_, dev_, 3) \ + RP_METHOD(prefix_, dev_, 4) \ + RP_METHOD(prefix_, dev_, 5) \ + RP_METHOD(prefix_, dev_, 6) \ + RP_METHOD(prefix_, dev_, 7) + +#endif /* defined(PIC_MODE) */ #define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ ACPI_DEV_IRQ(dev_, 0, a_), \ ACPI_DEV_IRQ(dev_, 1, b_), \ ACPI_DEV_IRQ(dev_, 2, c_), \ - ACPI_DEV_IRQ(dev_, 3, d_) + ACPI_DEV_IRQ(dev_, 3, d_), \ + +#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \ + ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ + ROOTPORT_METHODS(prefix_, dev_) + +#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \ + RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \ + RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \ + RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \ + RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \ + RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_) + +#define RP_METHOD(prefix_, dev_, func_)\ +Device(prefix_ ## 0 ## func_) \ +{ \ + Name(_ADR, dev_ ## 000 ## func_) \ + Name(_PRW, Package() { \ + 0, 0 \ + }) \ + Method(_PRT,0) { \ + If(PICM) { \ + Return (prefix_ ## func_ ## A) \ + } Else { \ + Return (prefix_ ## func_ ## P) \ + } \ + } \ +} /* Empty PIRQ_PIC definition. */ #define PIRQ_PIC(pirq_, pic_irq_) diff --git a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl b/src/soc/intel/fsp_baytrail/acpi/irqroute.asl index 940f853e5a..e6d7a5823d 100644 --- a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl +++ b/src/soc/intel/fsp_baytrail/acpi/irqroute.asl @@ -40,4 +40,11 @@ Method(_PRT) PCI_DEV_PIRQ_ROUTES }) } + } + +PCIE_BRIDGE_IRQ_ROUTES +#undef PIC_MODE +#include "irq_helper.h" +PCIE_BRIDGE_IRQ_ROUTES + diff --git a/src/soc/intel/fsp_baytrail/baytrail/irq.h b/src/soc/intel/fsp_baytrail/baytrail/irq.h index 98ca116c57..6f56b1ffd9 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/irq.h +++ b/src/soc/intel/fsp_baytrail/baytrail/irq.h @@ -160,6 +160,9 @@ extern const struct baytrail_irq_route global_baytrail_irq_route; #define PIRQ_PIC(pirq_, pic_irq_) \ [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ +/* used for ACPI only */ +#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) + #endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ #endif /* _BAYTRAIL_IRQ_H_ */ -- cgit v1.2.3