From cf270f0d62dbe2647a8e4b80d6c986a6922d47f9 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Thu, 30 Apr 2020 13:36:38 -0700 Subject: soc/intel/xeon_sp/cpx: Enable common P2SB Use common P2SB driver. This is needed to address a problem when enumerator does not see p2sb device (since it is hidden) but it is active and BAR is decoded. Change-Id: I9cb821a5684f15f1e1486872bf806a6ee3d0676f Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40920 Reviewed-by: Angel Pons Reviewed-by: Maxim Polyakov Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/Kconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 92681f2767..15669d1827 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -74,4 +74,7 @@ config FSP_TEMP_RAM_SIZE Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup. +config SOC_INTEL_COMMON_BLOCK_P2SB + def_bool y + endif -- cgit v1.2.3