From cb587a2522a9f5b68ee10e70832fa90eb84e6cc2 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Wed, 3 Jul 2019 16:50:17 +0530
Subject: drivers/intel: Move FSP stage_cache implementation into common block

Change-Id: Iebb6d698c236a95162b3c7eb07987483a293b50a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/soc/intel/common/block/smm/smm.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'src/soc/intel')

diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c
index 75b933e0e9..a2a7c164c8 100644
--- a/src/soc/intel/common/block/smm/smm.c
+++ b/src/soc/intel/common/block/smm/smm.c
@@ -18,10 +18,23 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
+#include <fsp/memmap.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/smm.h>
 #include <intelblocks/systemagent.h>
 #include <soc/pm.h>
+#include <stage_cache.h>
+
+#if !CONFIG(PLATFORM_USES_FSP1_1)
+void stage_cache_external_region(void **base, size_t *size)
+{
+	if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
+		printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
+		*base = NULL;
+		*size = 0;
+	}
+}
+#endif
 
 void smm_southbridge_clear_state(void)
 {
-- 
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