From c9bf446ee93fb2334117b97e8ed94b8f78e6856d Mon Sep 17 00:00:00 2001 From: Kein Yuan Date: Fri, 27 Jun 2014 09:12:57 -0700 Subject: baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPU Intel will be making slight changes to USB3 PLL VCO and iCLK PLL current on C0 stepping of BYT-M/D C0 stepping in order to meet the high demands for these processors. Pre-conversion materials are compatible with USB PLL VCO current increase. Post-conversion materials ARE REQUIRED to be run with increased USB3 PLL VCO current. BUG=chrome-os-partner:31199 TEST=Boot Rambi, then read USHPHY_CDN_PLL_CONTROL and verify register has new value. Signed-off-by: Stefan Reinauer Original-Commit-Id: bc01a3df80f5bd7fd86047c8bbf1584d19363e3b Original-Change-Id: Ie9c3d0afd54ea7ced2c76ebb948de95be0828fa0 Original-Signed-off-by: Kein Yuan Original-Reviewed-on: https://chromium-review.googlesource.com/211337 Original-Commit-Queue: Shawn Nematbakhsh Original-Tested-by: Shawn Nematbakhsh Original-Reviewed-by: Duncan Laurie Original-(cherry picked from commit df20eca47ca0ff33baf5d554ef11dd2b35706a5d) Original-Reviewed-on: https://chromium-review.googlesource.com/205970 Original-Reviewed-by: Shawn Nematbakhsh Original-Reviewed-on: https://chromium-review.googlesource.com/217772 Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Kenji Chen Original-Tested-by: Kenji Chen Change-Id: I1c825992a2b4dfac86f77cde567d2471ca4c19e6 Reviewed-on: http://review.coreboot.org/9200 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/baytrail/xhci.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 19339e4b62..21a0c5fcd9 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -27,6 +27,8 @@ #include #include +#include +#include #include #include #include @@ -227,6 +229,13 @@ static void xhci_init(device_t dev) else reg_script_run_on_dev(dev, xhci_init_boot_script); + /* C0 steppings change iCLK/USB PLL VCO settings from 5 to 7 */ + if (pattrs_get()->stepping == STEP_C0) { + uint32_t reg = iosf_ushphy_read(USHPHY_CDN_PLL_CONTROL); + reg |= 0x00700000; + iosf_ushphy_write(USHPHY_CDN_PLL_CONTROL, reg); + } + /* Finalize Initialization */ reg_script_run_on_dev(dev, xhci_hc_init); -- cgit v1.2.3