From c6589aefc16dc8911bc07c2fbdf2e81efe732796 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 28 Nov 2020 13:17:54 -0600 Subject: drivers/intel/gma: Include gfx.asl by default for all platforms... MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit which select INTEL_GMA_ACPI. Rework brightness level includes and platform-level asl files to avoid duplicate device definition for GFX0. Include gfx.asl for Skylake/Kabylake, since all other soc/intel/common platforms already do. Adjust mb/51nb/x210 to prevent device redefinition. Some OSes (e.g. Windows, MacOS) require/prefer the ACPI device for the IGD to exist, even if ACPI brightness controls are not utilized. This change adds a GFX0 ACPI device for all boards whose platforms select INTEL_GMA_ACPI without requiring non-functional brightness controls to be added at the board level. Change-Id: Ie71bd5fc7acd926b7ce7da17fbc108670fd453e0 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/48862 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/soc/intel/baytrail/acpi/southcluster.asl | 3 +++ src/soc/intel/braswell/acpi/southcluster.asl | 3 +++ src/soc/intel/broadwell/acpi/hostbridge.asl | 3 +++ src/soc/intel/skylake/acpi/pch.asl | 3 +++ 4 files changed, 12 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index e3997d75f7..f59f2406ef 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -256,3 +256,6 @@ Scope (\_SB.PCI0) // LPE Device #include "lpe.asl" } + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 2c31d40d22..d74647e98d 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -272,3 +272,6 @@ Scope (\_SB.PCI0) /* SCC Devices */ #include "scc.asl" } + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/soc/intel/broadwell/acpi/hostbridge.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl index 3e7ced0296..2b44c6522f 100644 --- a/src/soc/intel/broadwell/acpi/hostbridge.asl +++ b/src/soc/intel/broadwell/acpi/hostbridge.asl @@ -195,3 +195,6 @@ Device (PDRC) /* Configurable TDP */ #include "ctdp.asl" + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 6eea5bb53a..02e30f770f 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -65,3 +65,6 @@ Method (_OSC, 4) #if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) #include #endif + +/* Integrated graphics 0:2.0 */ +#include -- cgit v1.2.3