From c64a6d63ed9cbd20d8acd8d50ce76af275cca526 Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Fri, 23 Sep 2016 15:06:37 -0500
Subject: soc/intel/apollolake: provide power button ACPI device

Instead of having each mainboard provide the power button,
uncondtionally provide the power button ACPI device on behalf
of each mainboard.

BUG=chrome-os-partner:56677

Change-Id: I94c9e0353c8d829136f0d52a356286c6bedcddd5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16731
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
---
 src/soc/intel/apollolake/acpi/southbridge.asl | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'src/soc/intel')

diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index d7ced0f924..1c10f1a5ed 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -17,6 +17,15 @@
 
 #include <soc/gpe.h>
 
+/* Power button. */
+Scope (\_SB)
+{
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+	}
+}
+
 /* PCIE device */
 #include "pcie.asl"
 
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