From c0c477741d0089fb1eb83e4c88b6ad5ba1661cb9 Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Wed, 11 Aug 2021 21:33:53 +0530 Subject: soc/intel/alderlake: set default PL4 values for different SKUs Set default PL4 values for various Alder Lake CPU SKUs as per bug#191906315 comment#10. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board. Change-Id: I53791badbec3c165d56f20ce0656dc15d63bab37 Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/56917 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/chipset.cb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 2d5c54e4ae..05da658eac 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -5,21 +5,25 @@ chip soc/intel/alderlake register "power_limits_config[ADL_P_POWER_LIMITS_282_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 55, + .tdp_pl4 = 123, }" register "power_limits_config[ADL_P_POWER_LIMITS_482_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 64, + .tdp_pl4 = 140, }" register "power_limits_config[ADL_P_POWER_LIMITS_682_CORE]" = "{ .tdp_pl1_override = 45, .tdp_pl2_override = 115, + .tdp_pl4 = 215, }" register "power_limits_config[ADL_M_POWER_LIMITS_282_CORE]" = "{ .tdp_pl1_override = 9, .tdp_pl2_override = 30, + .tdp_pl4 = 68, }" device domain 0 on -- cgit v1.2.3