From bebb2a1705b697fccf91a0f2c3a9d5870a27e9fa Mon Sep 17 00:00:00 2001 From: "derek.huang" Date: Mon, 4 May 2020 18:09:36 +0800 Subject: soc/intel/tigerlake: update elog to include CSME reset causes Call out the CSME-initiated bits from HPR_CAUSE0 register and update the elog to include reset causes Change-Id: I32ffb55ff2ad26ec4e7609c41fc65e021a327a14 Signed-off-by: derek.huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/41026 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Nick Vaccaro --- src/soc/intel/tigerlake/elog.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 586dbfdd24..d5b875419a 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -61,6 +61,18 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps) if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) elog_add_event(ELOG_TYPE_THERM_TRIP); + /* CSME-Initiated Host Reset with power down */ + if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPD) + elog_add_event(ELOG_TYPE_MI_HRPD); + + /* CSME-Initiated Host Reset with power cycle */ + if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPC) + elog_add_event(ELOG_TYPE_MI_HRPC); + + /* CSME-Initiated Host Reset without power cycle */ + if (ps->hpr_cause0 & HPR_CAUSE0_MI_HR) + elog_add_event(ELOG_TYPE_MI_HR); + /* PWR_FLR Power Failure */ if (ps->gen_pmcon_a & PWR_FLR) elog_add_event(ELOG_TYPE_POWER_FAIL); -- cgit v1.2.3