From be291e8abf173e4f12e6d9e5532fdf1acbcb9a67 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 6 Jan 2019 07:35:11 +0100 Subject: soc/intel/fsp1.1: Implement postcar stage This moves FSP1.1 to use postcar stage to tear down CAR. On platforms with USE_GENERIC_FSP_CAR_INC the FSP header is found during the postcar stage so there is no need to push to save it in CAR global variables. On FSP1.1 platforms with an open source CAR implementation (Skylake, even though it still runs the FSP-T), the soc/intel/common/blocks/cpu/car/exit_car.S code tears down CAR. This also uses common functions to set up the MTRR to use after CAR is torn down. Test: build/boot on google/celes (BSW) and google/chell (SKL) Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30686 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- src/soc/intel/braswell/Makefile.inc | 2 ++ src/soc/intel/quark/include/soc/romstage.h | 2 +- src/soc/intel/quark/romstage/car_stage_entry.S | 6 ------ src/soc/intel/quark/romstage/fsp2_0.c | 3 +-- src/soc/intel/skylake/romstage/car_stage.S | 5 +++-- 5 files changed, 7 insertions(+), 11 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index e2b1fe5295..6b466c66f8 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -17,6 +17,8 @@ romstage-y += pmutil.c romstage-y += smbus.c romstage-y += tsc_freq.c +postcar-y += memmap.c +postcar-y += iosf.c postcar-y += tsc_freq.c ramstage-y += acpi.c diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index fb8a844815..c7de080146 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -25,7 +25,7 @@ #include #include -asmlinkage void *car_stage_c_entry(void); +asmlinkage void car_stage_c_entry(void); void clear_smi_and_wake_events(void); void disable_rom_shadow(void); void *locate_rmu_file(size_t *rmu_file_len); diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S index d51587143b..c9847eaac7 100644 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ b/src/soc/intel/quark/romstage/car_stage_entry.S @@ -29,12 +29,6 @@ car_stage_entry: /* Enter the C code */ call car_stage_c_entry -#if CONFIG(PLATFORM_USES_FSP1_1) -#if !ENV_VERSTAGE -#include "src/drivers/intel/fsp1_1/after_raminit.S" -#endif -#endif - /* The code should never reach this point */ movb $0x69, %ah jmp .Lhlt diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 31e130a398..2ec16c9f34 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -26,7 +26,7 @@ #include #include -asmlinkage void *car_stage_c_entry(void) +asmlinkage void car_stage_c_entry(void) { struct postcar_frame pcf; bool s3wake; @@ -83,7 +83,6 @@ asmlinkage void *car_stage_c_entry(void) postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH); run_postcar_phase(&pcf); - return NULL; } static struct chipset_power_state power_state CAR_GLOBAL; diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S index ee04f0272d..d8b45cb258 100644 --- a/src/soc/intel/skylake/romstage/car_stage.S +++ b/src/soc/intel/skylake/romstage/car_stage.S @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include + /* I/O delay between post codes on failure */ #define LHLT_DELAY 0x50000 @@ -20,9 +22,8 @@ .global car_stage_entry car_stage_entry: call romstage_c_entry - #include "src/drivers/intel/fsp1_1/after_raminit.S" - + /* we don't return here */ movb $0x69, %ah jmp .Lhlt -- cgit v1.2.3