From b6c32d7fe4ea98ba8b3a10cb5ce46448801855b8 Mon Sep 17 00:00:00 2001 From: Jamie Ryu Date: Wed, 3 Aug 2022 01:13:33 -0700 Subject: soc/intel/meteorlake: Enable GPIO 4 bits pad mode configuration This enables SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS to support 4 bits GPIO pad mode to configure native function 8 to 15. BUG=b:239690757 TEST=build and verify pad mode configuration with Meteor Lake mtlrvp Signed-off-by: Jamie Ryu Change-Id: Ibf4b13a3d19095d15bf857c7fe4ec0affb54a4e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66391 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal --- src/soc/intel/meteorlake/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 0550d734ef..f15871fe0b 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR + select SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT -- cgit v1.2.3