From b656e9b71e2ce494568ad1389b04b7dbb085d7ee Mon Sep 17 00:00:00 2001
From: Edward O'Callaghan <quasisec@google.com>
Date: Fri, 28 Aug 2020 19:28:01 +1000
Subject: PCI IDs: Add PCI ID for CML DPTF/DTT PCI device

This PCI ID is required in order for the CML devices to perform
SSDT generation for DPTF.

CML Processor, EDS, Vol 1,
Table 9-5, Section 9.2.

BUG=b:158986928
BRANCH=puff
TEST=builds

Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: I94aea6b9e0f60656827daada7b2cc2741604b8b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Andrew McRae <amcrae@google.com>
---
 src/soc/intel/common/block/dtt/dtt.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/soc/intel')

diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c
index f3969939c9..d92eb15c85 100644
--- a/src/soc/intel/common/block/dtt/dtt.c
+++ b/src/soc/intel/common/block/dtt/dtt.c
@@ -5,6 +5,7 @@
 #include <device/pci_ids.h>
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DEVICE_ID_INTEL_CML_DTT,
 	PCI_DEVICE_ID_INTEL_TGL_DTT,
 	PCI_DEVICE_ID_INTEL_JSL_DTT,
 };
-- 
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