From b57772d2bf117e81b9e3cbb9d08ffbfae581ba69 Mon Sep 17 00:00:00 2001 From: Barnali Sarkar Date: Mon, 2 Nov 2015 18:58:36 +0530 Subject: intel/skylake: Update UPD parameters as per FSP 1.8.0 Some MemoryInit UPD parameters have been moved to SiliconInit in FSP 1.8.0. This patch has the respective changes in coreboot for this. BRANCH=none BUG=none TEST=Build and booted in kunimitsu CQ-DEPEND=CL:*237423, CL:*237424 Change-Id: Ic008d22f96fb5f14965e5b5db15e05fb39dd52d3 Signed-off-by: Patrick Georgi Original-Commit-Id: 573c1d8325cd504213528030ecf99559402b5118 Original-Change-Id: I71b893aa7788519ed2ef15f3247945ffcbbbcf4d Original-Signed-off-by: Barnali Sarkar Original-Signed-off-by: Rizwan Qureshi Original-Reviewed-on: https://chromium-review.googlesource.com/310191 Original-Reviewed-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/12940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/skylake/chip.c | 173 ++++++++++++++++++++++++++++++ src/soc/intel/skylake/romstage/romstage.c | 171 ----------------------------- 2 files changed, 173 insertions(+), 171 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 1a8134cc70..01279b8a4d 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -299,6 +299,15 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) } } + memcpy(params->PcieRpEnable, config->PcieRpEnable, + sizeof(params->PcieRpEnable)); + memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, + sizeof(params->PcieRpClkReqSupport)); + memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, + sizeof(params->PcieRpClkReqNumber)); + + params->EnableLan = config->EnableLan; + params->Cio2Enable = config->Cio2Enable; params->SataSalpSupport = config->SataSalpSupport; params->SataPortsEnable[0] = config->SataPortsEnable[0]; params->SsicPortEnable = config->SsicPortEnable; @@ -390,6 +399,170 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, fsp_display_upd_value("Device4Enable", 1, original->Device4Enable, params->Device4Enable); + fsp_display_upd_value("PcieRpEnable[0]", 1, original->PcieRpEnable[0], + params->PcieRpEnable[0]); + fsp_display_upd_value("PcieRpEnable[1]", 1, original->PcieRpEnable[1], + params->PcieRpEnable[1]); + fsp_display_upd_value("PcieRpEnable[2]", 1, original->PcieRpEnable[2], + params->PcieRpEnable[2]); + fsp_display_upd_value("PcieRpEnable[3]", 1, original->PcieRpEnable[3], + params->PcieRpEnable[3]); + fsp_display_upd_value("PcieRpEnable[4]", 1, original->PcieRpEnable[4], + params->PcieRpEnable[4]); + fsp_display_upd_value("PcieRpEnable[5]", 1, original->PcieRpEnable[5], + params->PcieRpEnable[5]); + fsp_display_upd_value("PcieRpEnable[6]", 1, original->PcieRpEnable[6], + params->PcieRpEnable[6]); + fsp_display_upd_value("PcieRpEnable[7]", 1, original->PcieRpEnable[7], + params->PcieRpEnable[7]); + fsp_display_upd_value("PcieRpEnable[8]", 1, original->PcieRpEnable[8], + params->PcieRpEnable[8]); + fsp_display_upd_value("PcieRpEnable[9]", 1, original->PcieRpEnable[9], + params->PcieRpEnable[9]); + fsp_display_upd_value("PcieRpEnable[10]", 1, original->PcieRpEnable[10], + params->PcieRpEnable[10]); + fsp_display_upd_value("PcieRpEnable[11]", 1, original->PcieRpEnable[11], + params->PcieRpEnable[11]); + fsp_display_upd_value("PcieRpEnable[12]", 1, original->PcieRpEnable[12], + params->PcieRpEnable[12]); + fsp_display_upd_value("PcieRpEnable[13]", 1, original->PcieRpEnable[13], + params->PcieRpEnable[13]); + fsp_display_upd_value("PcieRpEnable[14]", 1, original->PcieRpEnable[14], + params->PcieRpEnable[14]); + fsp_display_upd_value("PcieRpEnable[15]", 1, original->PcieRpEnable[15], + params->PcieRpEnable[15]); + fsp_display_upd_value("PcieRpEnable[16]", 1, original->PcieRpEnable[16], + params->PcieRpEnable[16]); + fsp_display_upd_value("PcieRpEnable[17]", 1, original->PcieRpEnable[17], + params->PcieRpEnable[17]); + fsp_display_upd_value("PcieRpEnable[18]", 1, original->PcieRpEnable[18], + params->PcieRpEnable[18]); + fsp_display_upd_value("PcieRpEnable[19]", 1, original->PcieRpEnable[19], + params->PcieRpEnable[19]); + fsp_display_upd_value("PcieRpClkReqSupport[0]", 1, + original->PcieRpClkReqSupport[0], + params->PcieRpClkReqSupport[0]); + fsp_display_upd_value("PcieRpClkReqSupport[1]", 1, + original->PcieRpClkReqSupport[1], + params->PcieRpClkReqSupport[1]); + fsp_display_upd_value("PcieRpClkReqSupport[2]", 1, + original->PcieRpClkReqSupport[2], + params->PcieRpClkReqSupport[2]); + fsp_display_upd_value("PcieRpClkReqSupport[3]", 1, + original->PcieRpClkReqSupport[3], + params->PcieRpClkReqSupport[3]); + fsp_display_upd_value("PcieRpClkReqSupport[4]", 1, + original->PcieRpClkReqSupport[4], + params->PcieRpClkReqSupport[4]); + fsp_display_upd_value("PcieRpClkReqSupport[5]", 1, + original->PcieRpClkReqSupport[5], + params->PcieRpClkReqSupport[5]); + fsp_display_upd_value("PcieRpClkReqSupport[6]", 1, + original->PcieRpClkReqSupport[6], + params->PcieRpClkReqSupport[6]); + fsp_display_upd_value("PcieRpClkReqSupport[7]", 1, + original->PcieRpClkReqSupport[7], + params->PcieRpClkReqSupport[7]); + fsp_display_upd_value("PcieRpClkReqSupport[8]", 1, + original->PcieRpClkReqSupport[8], + params->PcieRpClkReqSupport[8]); + fsp_display_upd_value("PcieRpClkReqSupport[9]", 1, + original->PcieRpClkReqSupport[9], + params->PcieRpClkReqSupport[9]); + fsp_display_upd_value("PcieRpClkReqSupport[10]", 1, + original->PcieRpClkReqSupport[10], + params->PcieRpClkReqSupport[10]); + fsp_display_upd_value("PcieRpClkReqSupport[11]", 1, + original->PcieRpClkReqSupport[11], + params->PcieRpClkReqSupport[11]); + fsp_display_upd_value("PcieRpClkReqSupport[12]", 1, + original->PcieRpClkReqSupport[12], + params->PcieRpClkReqSupport[12]); + fsp_display_upd_value("PcieRpClkReqSupport[13]", 1, + original->PcieRpClkReqSupport[13], + params->PcieRpClkReqSupport[13]); + fsp_display_upd_value("PcieRpClkReqSupport[14]", 1, + original->PcieRpClkReqSupport[14], + params->PcieRpClkReqSupport[14]); + fsp_display_upd_value("PcieRpClkReqSupport[15]", 1, + original->PcieRpClkReqSupport[15], + params->PcieRpClkReqSupport[15]); + fsp_display_upd_value("PcieRpClkReqSupport[16]", 1, + original->PcieRpClkReqSupport[16], + params->PcieRpClkReqSupport[16]); + fsp_display_upd_value("PcieRpClkReqSupport[17]", 1, + original->PcieRpClkReqSupport[17], + params->PcieRpClkReqSupport[17]); + fsp_display_upd_value("PcieRpClkReqSupport[18]", 1, + original->PcieRpClkReqSupport[18], + params->PcieRpClkReqSupport[18]); + fsp_display_upd_value("PcieRpClkReqSupport[19]", 1, + original->PcieRpClkReqSupport[19], + params->PcieRpClkReqSupport[19]); + fsp_display_upd_value("PcieRpClkReqNumber[0]", 1, + original->PcieRpClkReqNumber[0], + params->PcieRpClkReqNumber[0]); + fsp_display_upd_value("PcieRpClkReqNumber[1]", 1, + original->PcieRpClkReqNumber[1], + params->PcieRpClkReqNumber[1]); + fsp_display_upd_value("PcieRpClkReqNumber[2]", 1, + original->PcieRpClkReqNumber[2], + params->PcieRpClkReqNumber[2]); + fsp_display_upd_value("PcieRpClkReqNumber[3]", 1, + original->PcieRpClkReqNumber[3], + params->PcieRpClkReqNumber[3]); + fsp_display_upd_value("PcieRpClkReqNumber[4]", 1, + original->PcieRpClkReqNumber[4], + params->PcieRpClkReqNumber[4]); + fsp_display_upd_value("PcieRpClkReqNumber[5]", 1, + original->PcieRpClkReqNumber[5], + params->PcieRpClkReqNumber[5]); + fsp_display_upd_value("PcieRpClkReqNumber[6]", 1, + original->PcieRpClkReqNumber[6], + params->PcieRpClkReqNumber[6]); + fsp_display_upd_value("PcieRpClkReqNumber[7]", 1, + original->PcieRpClkReqNumber[7], + params->PcieRpClkReqNumber[7]); + fsp_display_upd_value("PcieRpClkReqNumber[8]", 1, + original->PcieRpClkReqNumber[8], + params->PcieRpClkReqNumber[8]); + fsp_display_upd_value("PcieRpClkReqNumber[9]", 1, + original->PcieRpClkReqNumber[9], + params->PcieRpClkReqNumber[9]); + fsp_display_upd_value("PcieRpClkReqNumber[10]", 1, + original->PcieRpClkReqNumber[10], + params->PcieRpClkReqNumber[10]); + fsp_display_upd_value("PcieRpClkReqNumber[11]", 1, + original->PcieRpClkReqNumber[11], + params->PcieRpClkReqNumber[11]); + fsp_display_upd_value("PcieRpClkReqNumber[12]", 1, + original->PcieRpClkReqNumber[12], + params->PcieRpClkReqNumber[12]); + fsp_display_upd_value("PcieRpClkReqNumber[13]", 1, + original->PcieRpClkReqNumber[13], + params->PcieRpClkReqNumber[13]); + fsp_display_upd_value("PcieRpClkReqNumber[14]", 1, + original->PcieRpClkReqNumber[14], + params->PcieRpClkReqNumber[14]); + fsp_display_upd_value("PcieRpClkReqNumber[15]", 1, + original->PcieRpClkReqNumber[15], + params->PcieRpClkReqNumber[15]); + fsp_display_upd_value("PcieRpClkReqNumber[16]", 1, + original->PcieRpClkReqNumber[16], + params->PcieRpClkReqNumber[16]); + fsp_display_upd_value("PcieRpClkReqNumber[17]", 1, + original->PcieRpClkReqNumber[17], + params->PcieRpClkReqNumber[17]); + fsp_display_upd_value("PcieRpClkReqNumber[18]", 1, + original->PcieRpClkReqNumber[18], + params->PcieRpClkReqNumber[18]); + fsp_display_upd_value("PcieRpClkReqNumber[19]", 1, + original->PcieRpClkReqNumber[19], + params->PcieRpClkReqNumber[19]); + fsp_display_upd_value("EnableLan", 1, original->EnableLan, + params->EnableLan); + fsp_display_upd_value("Cio2Enable", 1, original->Cio2Enable, + params->Cio2Enable); fsp_display_upd_value("SataSalpSupport", 1, original->SataSalpSupport, params->SataSalpSupport); fsp_display_upd_value("SataPortsEnable[0]", 1, diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index a7fa6940d5..5481004121 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -85,22 +85,13 @@ void soc_memory_init_params(struct romstage_params *params, dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); config = dev->chip_info; - memcpy(upd->PcieRpEnable, config->PcieRpEnable, - sizeof(upd->PcieRpEnable)); - memcpy(upd->PcieRpClkReqSupport, config->PcieRpClkReqSupport, - sizeof(upd->PcieRpClkReqSupport)); - memcpy(upd->PcieRpClkReqNumber, config->PcieRpClkReqNumber, - sizeof(upd->PcieRpClkReqNumber)); - upd->MmioSize = 0x800; /* 2GB in MB */ upd->TsegSize = CONFIG_SMM_TSEG_SIZE; upd->IedSize = CONFIG_IED_REGION_SIZE; upd->ProbelessTrace = config->ProbelessTrace; - upd->EnableLan = config->EnableLan; upd->EnableTraceHub = config->EnableTraceHub; upd->SaGv = config->SaGv; upd->RMT = config->Rmt; - upd->Cio2Enable = config->Cio2Enable; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, @@ -227,169 +218,8 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, fsp_display_upd_value("IedSize", 4, old->IedSize, new->IedSize); fsp_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize); fsp_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize); - fsp_display_upd_value("EnableLan", 1, old->EnableLan, new->EnableLan); fsp_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub, new->EnableTraceHub); - fsp_display_upd_value("PcieRpEnable[0]", 1, old->PcieRpEnable[0], - new->PcieRpEnable[0]); - fsp_display_upd_value("PcieRpEnable[1]", 1, old->PcieRpEnable[1], - new->PcieRpEnable[1]); - fsp_display_upd_value("PcieRpEnable[2]", 1, old->PcieRpEnable[2], - new->PcieRpEnable[2]); - fsp_display_upd_value("PcieRpEnable[3]", 1, old->PcieRpEnable[3], - new->PcieRpEnable[3]); - fsp_display_upd_value("PcieRpEnable[4]", 1, old->PcieRpEnable[4], - new->PcieRpEnable[4]); - fsp_display_upd_value("PcieRpEnable[5]", 1, old->PcieRpEnable[5], - new->PcieRpEnable[5]); - fsp_display_upd_value("PcieRpEnable[6]", 1, old->PcieRpEnable[6], - new->PcieRpEnable[6]); - fsp_display_upd_value("PcieRpEnable[7]", 1, old->PcieRpEnable[7], - new->PcieRpEnable[7]); - fsp_display_upd_value("PcieRpEnable[8]", 1, old->PcieRpEnable[8], - new->PcieRpEnable[8]); - fsp_display_upd_value("PcieRpEnable[9]", 1, old->PcieRpEnable[9], - new->PcieRpEnable[9]); - fsp_display_upd_value("PcieRpEnable[10]", 1, old->PcieRpEnable[10], - new->PcieRpEnable[10]); - fsp_display_upd_value("PcieRpEnable[11]", 1, old->PcieRpEnable[11], - new->PcieRpEnable[11]); - fsp_display_upd_value("PcieRpEnable[12]", 1, old->PcieRpEnable[12], - new->PcieRpEnable[12]); - fsp_display_upd_value("PcieRpEnable[13]", 1, old->PcieRpEnable[13], - new->PcieRpEnable[13]); - fsp_display_upd_value("PcieRpEnable[14]", 1, old->PcieRpEnable[14], - new->PcieRpEnable[14]); - fsp_display_upd_value("PcieRpEnable[15]", 1, old->PcieRpEnable[15], - new->PcieRpEnable[15]); - fsp_display_upd_value("PcieRpEnable[16]", 1, old->PcieRpEnable[16], - new->PcieRpEnable[16]); - fsp_display_upd_value("PcieRpEnable[17]", 1, old->PcieRpEnable[17], - new->PcieRpEnable[17]); - fsp_display_upd_value("PcieRpEnable[18]", 1, old->PcieRpEnable[18], - new->PcieRpEnable[18]); - fsp_display_upd_value("PcieRpEnable[19]", 1, old->PcieRpEnable[19], - new->PcieRpEnable[19]); - fsp_display_upd_value("PcieRpClkReqSupport[0]", 1, - old->PcieRpClkReqSupport[0], - new->PcieRpClkReqSupport[0]); - fsp_display_upd_value("PcieRpClkReqSupport[1]", 1, - old->PcieRpClkReqSupport[1], - new->PcieRpClkReqSupport[1]); - fsp_display_upd_value("PcieRpClkReqSupport[2]", 1, - old->PcieRpClkReqSupport[2], - new->PcieRpClkReqSupport[2]); - fsp_display_upd_value("PcieRpClkReqSupport[3]", 1, - old->PcieRpClkReqSupport[3], - new->PcieRpClkReqSupport[3]); - fsp_display_upd_value("PcieRpClkReqSupport[4]", 1, - old->PcieRpClkReqSupport[4], - new->PcieRpClkReqSupport[4]); - fsp_display_upd_value("PcieRpClkReqSupport[5]", 1, - old->PcieRpClkReqSupport[5], - new->PcieRpClkReqSupport[5]); - fsp_display_upd_value("PcieRpClkReqSupport[6]", 1, - old->PcieRpClkReqSupport[6], - new->PcieRpClkReqSupport[6]); - fsp_display_upd_value("PcieRpClkReqSupport[7]", 1, - old->PcieRpClkReqSupport[7], - new->PcieRpClkReqSupport[7]); - fsp_display_upd_value("PcieRpClkReqSupport[8]", 1, - old->PcieRpClkReqSupport[8], - new->PcieRpClkReqSupport[8]); - fsp_display_upd_value("PcieRpClkReqSupport[9]", 1, - old->PcieRpClkReqSupport[9], - new->PcieRpClkReqSupport[9]); - fsp_display_upd_value("PcieRpClkReqSupport[10]", 1, - old->PcieRpClkReqSupport[10], - new->PcieRpClkReqSupport[10]); - fsp_display_upd_value("PcieRpClkReqSupport[11]", 1, - old->PcieRpClkReqSupport[11], - new->PcieRpClkReqSupport[11]); - fsp_display_upd_value("PcieRpClkReqSupport[12]", 1, - old->PcieRpClkReqSupport[12], - new->PcieRpClkReqSupport[12]); - fsp_display_upd_value("PcieRpClkReqSupport[13]", 1, - old->PcieRpClkReqSupport[13], - new->PcieRpClkReqSupport[13]); - fsp_display_upd_value("PcieRpClkReqSupport[14]", 1, - old->PcieRpClkReqSupport[14], - new->PcieRpClkReqSupport[14]); - fsp_display_upd_value("PcieRpClkReqSupport[15]", 1, - old->PcieRpClkReqSupport[15], - new->PcieRpClkReqSupport[15]); - fsp_display_upd_value("PcieRpClkReqSupport[16]", 1, - old->PcieRpClkReqSupport[16], - new->PcieRpClkReqSupport[16]); - fsp_display_upd_value("PcieRpClkReqSupport[17]", 1, - old->PcieRpClkReqSupport[17], - new->PcieRpClkReqSupport[17]); - fsp_display_upd_value("PcieRpClkReqSupport[18]", 1, - old->PcieRpClkReqSupport[18], - new->PcieRpClkReqSupport[18]); - fsp_display_upd_value("PcieRpClkReqSupport[19]", 1, - old->PcieRpClkReqSupport[19], - new->PcieRpClkReqSupport[19]); - fsp_display_upd_value("PcieRpClkReqNumber[0]", 1, - old->PcieRpClkReqNumber[0], - new->PcieRpClkReqNumber[0]); - fsp_display_upd_value("PcieRpClkReqNumber[1]", 1, - old->PcieRpClkReqNumber[1], - new->PcieRpClkReqNumber[1]); - fsp_display_upd_value("PcieRpClkReqNumber[2]", 1, - old->PcieRpClkReqNumber[2], - new->PcieRpClkReqNumber[2]); - fsp_display_upd_value("PcieRpClkReqNumber[3]", 1, - old->PcieRpClkReqNumber[3], - new->PcieRpClkReqNumber[3]); - fsp_display_upd_value("PcieRpClkReqNumber[4]", 1, - old->PcieRpClkReqNumber[4], - new->PcieRpClkReqNumber[4]); - fsp_display_upd_value("PcieRpClkReqNumber[5]", 1, - old->PcieRpClkReqNumber[5], - new->PcieRpClkReqNumber[5]); - fsp_display_upd_value("PcieRpClkReqNumber[6]", 1, - old->PcieRpClkReqNumber[6], - new->PcieRpClkReqNumber[6]); - fsp_display_upd_value("PcieRpClkReqNumber[7]", 1, - old->PcieRpClkReqNumber[7], - new->PcieRpClkReqNumber[7]); - fsp_display_upd_value("PcieRpClkReqNumber[8]", 1, - old->PcieRpClkReqNumber[8], - new->PcieRpClkReqNumber[8]); - fsp_display_upd_value("PcieRpClkReqNumber[9]", 1, - old->PcieRpClkReqNumber[9], - new->PcieRpClkReqNumber[9]); - fsp_display_upd_value("PcieRpClkReqNumber[10]", 1, - old->PcieRpClkReqNumber[10], - new->PcieRpClkReqNumber[10]); - fsp_display_upd_value("PcieRpClkReqNumber[11]", 1, - old->PcieRpClkReqNumber[11], - new->PcieRpClkReqNumber[11]); - fsp_display_upd_value("PcieRpClkReqNumber[12]", 1, - old->PcieRpClkReqNumber[12], - new->PcieRpClkReqNumber[12]); - fsp_display_upd_value("PcieRpClkReqNumber[13]", 1, - old->PcieRpClkReqNumber[13], - new->PcieRpClkReqNumber[13]); - fsp_display_upd_value("PcieRpClkReqNumber[14]", 1, - old->PcieRpClkReqNumber[14], - new->PcieRpClkReqNumber[14]); - fsp_display_upd_value("PcieRpClkReqNumber[15]", 1, - old->PcieRpClkReqNumber[15], - new->PcieRpClkReqNumber[15]); - fsp_display_upd_value("PcieRpClkReqNumber[16]", 1, - old->PcieRpClkReqNumber[16], - new->PcieRpClkReqNumber[16]); - fsp_display_upd_value("PcieRpClkReqNumber[17]", 1, - old->PcieRpClkReqNumber[17], - new->PcieRpClkReqNumber[17]); - fsp_display_upd_value("PcieRpClkReqNumber[18]", 1, - old->PcieRpClkReqNumber[18], - new->PcieRpClkReqNumber[18]); - fsp_display_upd_value("PcieRpClkReqNumber[19]", 1, - old->PcieRpClkReqNumber[19], - new->PcieRpClkReqNumber[19]); fsp_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc, new->IgdDvmt50PreAlloc); fsp_display_upd_value("InternalGfx", 1, old->InternalGfx, @@ -398,7 +228,6 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, new->ApertureSize); fsp_display_upd_value("SaGv", 1, old->SaGv, new->SaGv); fsp_display_upd_value("RMT", 1, old->RMT, new->RMT); - fsp_display_upd_value("Cio2Enable", 1, old->Cio2Enable, new->Cio2Enable); } /* SOC initialization after RAM is enabled. */ -- cgit v1.2.3