From b525ea726b257ca6b4e03f4f4427f92046722e26 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 20 Sep 2022 18:07:56 +0000 Subject: Revert "soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown" This reverts commit 7ef5376123d4d0ebb811795fcee1de7066f65a0f. Reason for revert: It was merged before its dependencies so now master is broken. Change-Id: Ia270efaed4f5c9d0c7b9761ae22dec55f57f74cf Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/67285 Reviewed-by: Felix Singer Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/chip.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 5bee9bfdbb..da2d00adb7 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -698,13 +697,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); - /* coreboot handles the lockdown */ - silconfig->LockDownGlobalSmi = 0; - silconfig->BiosLock = 0; - silconfig->BiosInterface = 0; - silconfig->WriteProtectionEnable[0] = 0; - silconfig->SpiEiss = 0; - silconfig->RtcLock = 0; + /* Disable setting of EISS bit in FSP. */ + silconfig->SpiEiss = 0; + + /* Disable FSP from locking access to the RTC NVRAM */ + silconfig->RtcLock = 0; /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; -- cgit v1.2.3