From b27cfd62b20dd526fc2b7413aac10fbed8e2cb9a Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 20 Dec 2023 20:36:05 +0530 Subject: soc/intel/cmn/block/smm: Clear SPI SYNC_SS before disabling WPD This patch follows the BWG recommendation (doc 729123) by clearing the SPI SYNC_SS bit before disabling the WPD bit in SPI_BIOS_CONTROL. This prevents boot hangs due to a 3-strike error. Unable to follow this guideline would result into boot hang (3-strike error). BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex. Change-Id: I18dbbc92554d803eea38ceb0b936a9da9191cb11 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/79662 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/soc/intel/common/block/smm/smihandler.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 680ec87f3e..6c271968c1 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -297,9 +297,13 @@ static void southbridge_smi_store( const bool wp_enabled = !fast_spi_wpd_status(); if (wp_enabled) { set_insmm_sts(true); - fast_spi_disable_wp(); - /* Not clearing SPI sync SMI status here results in hangs */ + /* + * As per BWG, clearing "SPI_BIOS_CONTROL_SYNC_SS" + * bit is a must prior setting SPI_BIOS_CONTROL_WPD" bit + * to avoid 3-strike error. + */ fast_spi_clear_sync_smi_status(); + fast_spi_disable_wp(); } /* drivers/smmstore/smi.c */ -- cgit v1.2.3