From acfc149f7b16ef40816e3d5d4c2f8452fe9dd091 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Thu, 6 Jul 2017 15:27:27 -0700 Subject: soc/intel/cannonlake: Add microcode support Microcode needs to be loaded prior to FSP initialization. Change-Id: Idd70bd3e6555866d9bb232e8904aed4120c79fe7 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/20484 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/Kconfig | 2 ++ src/soc/intel/cannonlake/Makefile.inc | 1 + 2 files changed, 3 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index b3f657e0bd..2c60309e6d 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select REG_SCRIPT select C_ENVIRONMENT_BOOTBLOCK + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select HAVE_HARD_RESET select HAVE_INTEL_FIRMWARE select INTEL_CAR_NEM_ENHANCED @@ -36,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_GPIO + select SUPPORT_CPU_UCODE_IN_CBFS config UART_DEBUG bool "Enable UART debug port." diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8afd7ce306..27c2e9b864 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y) +subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/tsc -- cgit v1.2.3