From a963acdcc70747911981afcd1474d39d75ca8804 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Fri, 16 Aug 2019 20:34:25 +0300
Subject: arch/x86: Add <arch/romstage.h>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Start with moving all postcar_frame related function
declarations here from <arch/cpu.h>.

Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/apollolake/romstage.c             | 1 +
 src/soc/intel/baytrail/romstage/romstage.c      | 1 +
 src/soc/intel/broadwell/romstage/romstage.c     | 2 +-
 src/soc/intel/cannonlake/romstage/romstage.c    | 1 +
 src/soc/intel/denverton_ns/romstage.c           | 1 +
 src/soc/intel/icelake/romstage/romstage.c       | 1 +
 src/soc/intel/quark/romstage/fsp2_0.c           | 1 +
 src/soc/intel/skylake/romstage/romstage_fsp20.c | 1 +
 8 files changed, 8 insertions(+), 1 deletion(-)

(limited to 'src/soc/intel')

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index fb8473c512..1464d2c6b3 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -17,6 +17,7 @@
  */
 
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <device/pci_ops.h>
 #include <arch/symbols.h>
 #include <assert.h>
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 63e36aaa36..f20c363a35 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -16,6 +16,7 @@
 #include <stddef.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
+#include <arch/romstage.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <bootblock_common.h>
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index e7b8ae0180..3f264ff5ec 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -16,7 +16,7 @@
 #include <stddef.h>
 #include <stdint.h>
 #include <arch/cbfs.h>
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <bootblock_common.h>
 #include <bootmode.h>
 #include <cbmem.h>
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 94b9899422..9f02c8b1d3 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -14,6 +14,7 @@
  */
 
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <cbmem.h>
 #include <console/console.h>
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index 53c51f488c..9c41486aa2 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -15,6 +15,7 @@
  */
 
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <arch/io.h>
 #include <cbmem.h>
 #include <cf9_reset.h>
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
index 65e65cc80e..8312f178e4 100644
--- a/src/soc/intel/icelake/romstage/romstage.c
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -14,6 +14,7 @@
  */
 
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <cbmem.h>
 #include <console/console.h>
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index 20f2ad776b..0489621045 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -14,6 +14,7 @@
  */
 
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <arch/symbols.h>
 #include <console/console.h>
 #include <cbmem.h>
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 221c6c41d5..8b5cd18195 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -14,6 +14,7 @@
  */
 
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <arch/symbols.h>
 #include <assert.h>
 #include <cpu/x86/mtrr.h>
-- 
cgit v1.2.3