From a421b1a289fd173da609a4d1e2625c44ad1faad4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 9 Jan 2022 02:14:38 +0100 Subject: soc/intel/tgl/pcie_rp: correct root port map MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TGL-LP only has 12 root ports, not 20. Correct the port map. Change-Id: I3f5c69a2e7e3a2b8292c81beeac4ea6c7279d4b4 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/60943 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Tim Wawrzynczak Reviewed-by: Felix Singer --- src/soc/intel/tigerlake/pcie_rp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/tigerlake/pcie_rp.c b/src/soc/intel/tigerlake/pcie_rp.c index ceb85d8aed..5966af6c2b 100644 --- a/src/soc/intel/tigerlake/pcie_rp.c +++ b/src/soc/intel/tigerlake/pcie_rp.c @@ -8,8 +8,7 @@ static const struct pcie_rp_group pch_lp_rp_groups[] = { { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, - { .slot = PCH_DEV_SLOT_PCIE_2, .count = 4 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, { 0 } }; -- cgit v1.2.3