From a247319ebeb274bb84e1512688ac179d38a40c32 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 22 Feb 2023 13:03:04 +0000 Subject: soc/intel/{adl, cmn, mtl}: Refactor MP Init related configs This patch optimizes CPU MP Init related configs being used within multiple SoC directory and moving essential configs into common code to let the SoC user to choose as per the requirement. TEST=Able to build and boot google/kano and google/rex. Signed-off-by: Subrata Banik Change-Id: I12adcc04e84244656a0d2dcf97607bd036320887 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73196 Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Tarun Tuli --- src/soc/intel/alderlake/Kconfig | 26 +------------------------- src/soc/intel/alderlake/fsp_params.c | 2 +- src/soc/intel/common/block/cpu/Kconfig | 24 ++++++++++++++++++++++++ src/soc/intel/meteorlake/Kconfig | 26 +------------------------- src/soc/intel/meteorlake/fsp_params.c | 2 +- 5 files changed, 28 insertions(+), 52 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 27176ec9c9..dd6bb22952 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -75,6 +75,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select INTEL_GMA_OPREGION_2_1 select INTEL_TXT_LIB + select MP_SERVICES_PPI_V2 select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_2 @@ -476,31 +477,6 @@ config USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS Note: selection of this config would introduce an additional warm reset in cold-reset scenarios due to function disabling of the UFS controller. -choice - prompt "Multiprocessor (MP) Initialization configuration to use" - default USE_FSP_MP_INIT - -config USE_FSP_MP_INIT - bool "Use FSP MP init" - select MP_SERVICES_PPI_V2 - help - Upon selection, coreboot brings APs from reset and the FSP runs feature programming. - -config USE_COREBOOT_MP_INIT - bool "Use coreboot MP init" - # FSP assumes ownership of the APs (Application Processors) - # upon passing `NULL` pointer to the CpuMpPpi FSP-S UPD. - # Hence, select `MP_SERVICES_PPI_V2_NOOP` config to pass a valid - # pointer to the CpuMpPpi UPD with FSP_UNSUPPORTED type APIs. - # This will protect APs from getting hijacked by FSP while coreboot - # decides to set SkipMpInit UPD. - select MP_SERVICES_PPI_V2_NOOP - select RELOAD_MICROCODE_PATCH - help - Upon selection, coreboot performs MP Init. - -endchoice - if STITCH_ME_BIN config CSE_BPDT_VERSION diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index aa8de99391..704f910a69 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -597,7 +597,7 @@ static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, */ s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); - if (CONFIG(USE_FSP_MP_INIT)) + if (CONFIG(USE_FSP_FEATURE_PROGRAM_ON_APS)) /* * Fill `2nd microcode loading FSP UPD` if FSP is running CPU feature * programming. diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 132480482a..8b30dcf12c 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -18,6 +18,30 @@ config SOC_INTEL_COMMON_BLOCK_CPU_MPINIT ensured that all MTRRs are re-programmed based on the DRAM resource settings. +choice + prompt "Application Processors (AP) Feature Programming Configuration to use" + default USE_FSP_FEATURE_PROGRAM_ON_APS if MP_SERVICES_PPI_V1 || MP_SERVICES_PPI_V2 + default USE_COREBOOT_MP_INIT if MP_SERVICES_PPI_V2_NOOP + +config USE_FSP_FEATURE_PROGRAM_ON_APS + bool "Allow FSP running CPU feature programming on MP init" + help + Upon selection, coreboot brings APs from reset and the FSP runs feature programming. + +config USE_COREBOOT_MP_INIT + bool "Use coreboot MP init" + # FSP assumes ownership of the APs (Application Processors) + # upon passing `NULL` pointer to the CpuMpPpi FSP-S UPD. + # Hence, select `MP_SERVICES_PPI_V2_NOOP` config to pass a valid + # pointer to the CpuMpPpi UPD with FSP_UNSUPPORTED type APIs. + # This will protect APs from getting hijacked by FSP while coreboot + # decides to set SkipMpInit UPD. + select RELOAD_MICROCODE_PATCH + help + Upon selection, coreboot performs MP Init. + +endchoice + config SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE bool depends on SOC_INTEL_COMMON_BLOCK_CPU diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 03782ddaaa..27d154b754 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_OPREGION_2_1 select IOAPIC select MICROCODE_BLOB_UNDISCLOSED + select MP_SERVICES_PPI_V2 select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_3 @@ -345,31 +346,6 @@ config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET hex default 0x800000 -choice - prompt "Multiprocessor (MP) Initialization configuration to use" - default MTL_USE_FSP_MP_INIT - -config MTL_USE_FSP_MP_INIT - bool "Use FSP MP init" - select MP_SERVICES_PPI_V2 - help - Upon selection, coreboot brings APs from reset and the FSP runs feature programming. - -config MTL_USE_COREBOOT_MP_INIT - bool "Use coreboot MP init" - # FSP assumes ownership of the APs (Application Processors) - # upon passing `NULL` pointer to the CpuMpPpi FSP-S UPD. - # Hence, select `MP_SERVICES_PPI_V2_NOOP` config to pass a valid - # pointer to the CpuMpPpi UPD with FSP_UNSUPPORTED type APIs. - # This will protect APs from getting hijacked by FSP while coreboot - # decides to set SkipMpInit UPD. - select MP_SERVICES_PPI_V2_NOOP - select RELOAD_MICROCODE_PATCH - help - Upon selection, coreboot performs MP Initialization that includes feature programming. - -endchoice - config FSP_PUBLISH_MBP_HOB bool default n if CHROMEOS diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index fae9cbb1b1..041429dcc4 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -389,7 +389,7 @@ static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, * Fill `2nd microcode loading FSP UPD` if FSP is running CPU feature * programming. */ - if (CONFIG(MTL_USE_FSP_MP_INIT)) + if (CONFIG(USE_FSP_FEATURE_PROGRAM_ON_APS)) fill_fsps_microcode_params(s_cfg, config); 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