From 9b5b17feca7d970879230e35941645abf7ff926c Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Sat, 5 Feb 2022 19:40:01 +0530 Subject: soc/intel/alderlake: Define USB2_PORT_MAX_TYPE_C macro The patch defines USB2_PORT_MAX_TYPE_C macro to allow mark the type_c flag.The USB2_PORT_MAX_TYPE_C macro modifies the USB2 configuration to indicate the port mapped to Type-C and sets Max TX and Pre-emp settings. This is an extension to existing macro USB2_PORT_MAX. The change is required to enable port reset event on a USB2 port. This event is passed to USB3 upstream ports to upgrade back to super speed (USB3) after a downgrade during low power state. BUG=b:193287279 TEST=Build the code for Gimble board Signed-off-by: Sridhar Siricilla Change-Id: I464f139d8e367907191c04f9170ac53d327776ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/61623 Reviewed-by: Rizwan Qureshi Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/include/soc/usb.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h index 70a367ec59..0eb616055c 100644 --- a/src/soc/intel/alderlake/include/soc/usb.h +++ b/src/soc/intel/alderlake/include/soc/usb.h @@ -104,6 +104,17 @@ enum { .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ } +/* Type-C Port, Max TX and Pre-emp settings */ +#define USB2_PORT_MAX_TYPE_C(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_56P3MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + .type_c = 1, \ +} + /* Type-C Port, no BC1.2 charge detect module / MUX * Length = 3.0" - 9.00" */ #define USB2_PORT_TYPE_C(pin) { \ -- cgit v1.2.3