From 996bab4a2096d47be0a60e9930f0b10d62eec5ed Mon Sep 17 00:00:00 2001
From: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Date: Fri, 5 Feb 2021 12:03:19 +0530
Subject: soc/intel/alderlake: Increase VBT size to 9 KiB

Alderlake includes latest VBT (version 237 onwards),which has size of
8.5 KiB. This change is specific to alderlake so utilizing Kconfig option
to increase VBT size specifically for ADL platforms.

BUG=None
BRANCH=None
TEST=Include new VBT and boot the platform. Able to see firmware screen

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
---
 src/soc/intel/alderlake/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/soc/intel')

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index ec79855074..1c694544b0 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -198,6 +198,10 @@ config CONSOLE_UART_BASE_ADDRESS
 	default 0xfe03e000
 	depends on INTEL_LPSS_UART_FOR_CONSOLE
 
+config VBT_DATA_SIZE_KB
+	int
+	default 9
+
 # Clock divider parameters for 115200 baud rate
 # Baudrate = (UART source clcok * M) /(N *16)
 # ADL UART source clock: 120MHz
-- 
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