From 93d215cb05a05464fef14f26f638341da2ce3d59 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Sat, 2 Nov 2019 12:14:06 +0100 Subject: soc/intel/cannonlake: add soc implementation for ETR address API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add soc implementation for the new ETR address API. Change-Id: Ifc128099185a2c40ec3e7c5f84fcc42227c93f28 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36567 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/pmutil.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index a543861406..428a89fe4b 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -172,6 +172,11 @@ uintptr_t soc_read_pmc_base(void) return (uintptr_t)pmc_mmio_regs(); } +uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_cannonlake_config *config; -- cgit v1.2.3