From 9355f318faceee026abc2dd7b57f8927df286ff7 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 16 Mar 2024 18:06:02 +0530 Subject: soc/intel/cmn/ramtop: Refactor MTRR handling for RAMTOP range This patch refactors RAMTOP MTRR type selection to address a critical NEM logic bug on SoCs with non-power-of-two cache sets. This bug can cause runtime hangs when Write Back (WB) caching is enabled. Workaround: Force MTRR type to WC (Write Combining) on affected SoCs when the cache set count is not a power of two. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot on google/ovis and google/rex (including Ovis with non-power-of-two cache configuration). Change-Id: Ia9a8f0d37d581b05c19ea7f9b1a07933caa956d4 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/81269 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/soc/intel/common/basecode/ramtop/ramtop.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/common/basecode/ramtop/ramtop.c b/src/soc/intel/common/basecode/ramtop/ramtop.c index ec326bb1c0..9cef9b1358 100644 --- a/src/soc/intel/common/basecode/ramtop/ramtop.c +++ b/src/soc/intel/common/basecode/ramtop/ramtop.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -125,9 +126,24 @@ void early_ramtop_enable_cache_range(void) printk(BIOS_WARNING, "ramtop_table update failure due to no free MTRR available!\n"); return; } + + /* + * Background: Some SoCs have a critical bug inside the NEM logic which is responsible + * for mapping cached memory to physical memory during tear down and + * eventually malfunctions if the number of cache sets is not a power of two. + * This can lead to runtime hangs. + * + * Workaround: To mitigate this issue on affected SoCs, we force the MTRR type to + * WC (Write Combining) unless the cache set count is a power of two. + * This change alters caching behavior but prevents the runtime failures. + */ + unsigned int mtrr_type = MTRR_TYPE_WRCOMB; /* * We need to make sure late romstage (including FSP-M post mem) will be run * cached. Caching 16MB below ramtop is a safe to cover late romstage. */ - set_var_mtrr(mtrr, ramtop - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); + if (is_cache_sets_power_of_two()) + mtrr_type = MTRR_TYPE_WRBACK; + + set_var_mtrr(mtrr, ramtop - 16 * MiB, 16 * MiB, mtrr_type); } -- cgit v1.2.3