From 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e Mon Sep 17 00:00:00 2001 From: Scott Radcliffe Date: Fri, 10 Oct 2014 16:09:52 -0400 Subject: intel/fsp_baytrail: Add padding so device_nvs location matches ACPI The offset of the device_nvs in the gnvs struct is expected to be 0x1000. It is actually 0x100 so padding is needed to move device_nvs to the expected location. ACPI references to device_nvs objects will be correct with the padding. This was tested using a Micro Industries customized Baytrail-I board based on the Intel Bayley Bay CRB. In intel/baytrail/nvs.h, there's a Google customized structure located at 0x0100-0x0FFF that is removed from the fsp_baytrail/nvs.h which explains the mismatch here. Change-Id: I4721a79b53b5b3345ff9b0c053bdd31d2cf9cb61 Signed-off-by: Scott Radcliffe Reviewed-on: http://review.coreboot.org/7038 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/soc/intel/fsp_baytrail/baytrail/nvs.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/fsp_baytrail/baytrail/nvs.h b/src/soc/intel/fsp_baytrail/baytrail/nvs.h index 53c4a64887..242f6d3ab5 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/nvs.h +++ b/src/soc/intel/fsp_baytrail/baytrail/nvs.h @@ -61,6 +61,9 @@ typedef struct { u32 cbmc; /* 0x38 - coreboot memconsole */ u8 rsvd3[196]; + /* Pad 0x0100-0x0fff */ + u8 rsvd4[3840]; + /* Baytrail LPSS (0x1000) */ device_nvs_t dev; } __attribute__((packed)) global_nvs_t; -- cgit v1.2.3