From 8bf69d307892c65cdc604136146c1a6702956e20 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Thu, 9 Mar 2017 13:43:54 +0530
Subject: soc/intel/apollolake: Use RTC common code

This patch uses common RTC library to enable
upper 128 byte bank of RTC RAM.

Change-Id: I55e196f6c5282d7c0a31b3980da8ae71764df611
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18700
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
---
 src/soc/intel/apollolake/Kconfig               |  1 +
 src/soc/intel/apollolake/bootblock/bootblock.c | 12 ++----------
 2 files changed, 3 insertions(+), 10 deletions(-)

(limited to 'src/soc/intel')

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index c1ce9d729e..b8af418289 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -55,6 +55,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_PCR
 	select SOC_INTEL_COMMON_BLOCK_SA
+	select SOC_INTEL_COMMON_BLOCK_RTC
 	select SOC_INTEL_COMMON_LPSS_I2C
 	select SOC_INTEL_COMMON_SMI
 	select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 450cd2034b..62fe47b3eb 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -20,6 +20,7 @@
 #include <device/pci.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/systemagent.h>
+#include <intelblocks/rtc.h>
 #include <lib.h>
 #include <soc/iomap.h>
 #include <soc/cpu.h>
@@ -28,15 +29,11 @@
 #include <soc/mmap_boot.h>
 #include <soc/systemagent.h>
 #include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
 #include <soc/pm.h>
 #include <soc/uart.h>
 #include <spi-generic.h>
 #include <timestamp.h>
 
-#define PCR_RTC_CONF		0x3400
-#define PCR_RTC_CONF_UCMOS_EN	0x4
-
 static const struct pad_config tpm_spi_configs[] = {
 	PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3),	/* FST_SPI_CS2_N */
 };
@@ -47,11 +44,6 @@ static void tpm_enable(void)
 	gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
 }
 
-static void enable_cmos_upper_bank(void)
-{
-	pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN);
-}
-
 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {
 	device_t dev;
@@ -71,7 +63,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 	pci_write_config16(dev, PCI_COMMAND,
 				PCI_COMMAND_IO | PCI_COMMAND_MASTER);
 
-	enable_cmos_upper_bank();
+	enable_rtc_upper_bank();
 
 	/* Call lib/bootblock.c main */
 	bootblock_main_with_timestamp(base_timestamp);
-- 
cgit v1.2.3