From 88e85b3de4ab29dca048251885815a29031948e5 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Fri, 4 Dec 2020 14:59:00 +0100 Subject: soc/intel/skl: set PEG port state to auto MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Setting PegXEnable to 1, statically enables the PEG ports, which blocks the SoC from going to deeper PC states. Instead, set the state to "auto" (2), so the port gets disabled, when no device was detected. Note: Currently, this only works with the AST PCI bridge disabled or the VGA jumper set to disabled on coreboot, while it works on vendor in any case. The reason for this is still unclear. Test: powertop on X11SSM-F shows SoC in PC8 like on vendor firmware instead of just PC3 Signed-off-by: Michael Niewöhner Change-Id: I3933a219b77d7234af273217df031cf627b4071f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48304 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/romstage/romstage.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 5e0d6871e2..a7ce2f8de5 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -173,6 +173,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */ m_cfg->Peg0Enable = dev && dev->enabled; if (m_cfg->Peg0Enable) { + m_cfg->Peg0Enable = 2; m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth; /* Use maximum possible link speed */ m_cfg->Peg0MaxLinkSpeed = 0; @@ -186,6 +187,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */ m_cfg->Peg1Enable = dev && dev->enabled; if (m_cfg->Peg1Enable) { + m_cfg->Peg1Enable = 2; m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth; m_cfg->Peg1MaxLinkSpeed = 0; m_cfg->Peg1PowerDownUnusedLanes = 1; @@ -196,6 +198,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */ m_cfg->Peg2Enable = dev && dev->enabled; if (m_cfg->Peg2Enable) { + m_cfg->Peg2Enable = 2; m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth; m_cfg->Peg2MaxLinkSpeed = 0; m_cfg->Peg2PowerDownUnusedLanes = 1; -- cgit v1.2.3