From 87aecf811dcf56fa326dc644da4c29e453167cce Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sat, 25 Jul 2020 10:03:37 +0200 Subject: soc/intel/skylake: Enable TraceHub depending on devicetree configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently TraceHub gets enabled by the option EnableTraceHub, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the TraceHub controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableTraceHub setting. Change-Id: Idcd1e5035bc66c48620e4033d8b4988428e63db9 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/43847 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/chip.h | 1 - src/soc/intel/skylake/romstage/romstage.c | 4 +++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 243e6ee851..f670e0878f 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -175,7 +175,6 @@ struct soc_intel_skylake_config { u8 IoBufferOwnership; /* Trace Hub function */ - u8 EnableTraceHub; u32 TraceHubMemReg0Size; u32 TraceHubMemReg1Size; diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 8e789bce80..76f7a7304c 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -293,7 +293,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) /* DCI and TraceHub configs */ m_t_cfg->PchDciEn = config->PchDciEn; - m_cfg->EnableTraceHub = config->EnableTraceHub; + + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + m_cfg->EnableTraceHub = dev ? dev->enabled : 0; m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; -- cgit v1.2.3