From 85e3c77226e1b95c6878d238b60ec144293de91b Mon Sep 17 00:00:00 2001 From: Hannah Williams Date: Wed, 25 May 2016 11:12:43 -0700 Subject: soc/apollolake: remove _RMV and _DSW methods from xhci.asl Change-Id: Ic314656f34fda10e58e55bdefeb0a1f0c6ab5ae2 Signed-off-by: Hannah Williams Reviewed-on: https://review.coreboot.org/14966 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/apollolake/acpi/xhci.asl | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index fc67074a8a..c07c7079ad 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -1,4 +1,5 @@ -/* This file is part of the coreboot project. +/* + * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corporation. * @@ -13,29 +14,18 @@ */ /* XHCI Controller 0:15.0 */ -Device(XHC1) { - Name(_ADR, 0x00150000) // Device 21, Function 0 +Device (XHC1) { + Name (_ADR, 0x00150000) /* Device 21, Function 0 */ Name (_S3D, 3) /* D3 supported in S3 */ Name (_S0W, 3) /* D3 can wake device in S0 */ Name (_S3W, 3) /* D3 can wake system from S3 */ - // Declare XHCI GPE status and enable bits are bit 13 + /* Declare XHCI GPE status and enable bits are bit 13 */ Name (_PRW, Package() { GPE0A_XHCI_PME_STS, 3 }) - Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake - { - Return (Zero) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - Return (Zero) - } - - Method(_STA, 0) + Method (_STA, 0) { Return (0xF) } - } -- cgit v1.2.3