From 815d96a975d67db73b8299b3c521b74cf9725b99 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 21 Jan 2020 21:51:19 -0800 Subject: soc/intel/tigerlake: Enable SATA Configure SATA FSP UPD according to mainboard design. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory Signed-off-by: Wonkyu Kim Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38504 Reviewed-by: Nick Vaccaro Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/fsp_params_tgl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index fe59ac1d42..305748e8f3 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -121,6 +121,20 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* PCH UART selection for FSP Debug */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + /* SATA */ + dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); + if (!dev) + params->SataEnable = 0; + else { + params->SataEnable = dev->enabled; + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + } + mainboard_silicon_init_params(params); } -- cgit v1.2.3