From 7c9a0e8a9cfa90f8f413f3b485f8103bca80fac6 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 23 Oct 2019 17:02:50 +0200 Subject: arch/x86: Use the stage argument to implement cbmem_top Currently all stages that need cbmem need an implementation of a cbmem_top function. On FSP and AGESA platforms this proves to be painful and a pointer to the top of lower memory if often passed via lower memory (e.g. EBDA) or via a PCI scratchpad register. The problem with writing to lower memory is that also need to be written on S3 as one cannot assume it to be still there. Writing things on S3 is always a fragile thing to do. A very generic solution is to pass cbmem_top via the program argument. It should be possible to implement this solution on every architecture. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. TESTED on qemu-x86. Change-Id: I6d5a366d6f1bc76f26d459628237e6b2c8ae03ea Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36144 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/intel/quark/Makefile.inc | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index cff089149d..3a58cc9235 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -41,7 +41,6 @@ romstage-y += reset.c postcar-y += fsp_params.c postcar-y += i2c.c -postcar-y += memmap.c postcar-y += reg_access.c postcar-y += tsc_freq.c postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c @@ -53,7 +52,6 @@ ramstage-y += fsp_params.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c ramstage-y += lpc.c -ramstage-y += memmap.c ramstage-y += northcluster.c ramstage-y += reg_access.c ramstage-y += reset.c -- cgit v1.2.3