From 7ace555cc112c6942814eb28496c8d9cd119da78 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 15 Jan 2019 10:58:30 +0100 Subject: soc/intel/fsp_broadwell_de: Fix TSEG size computation The address bits 19:0 of TSEG_LIMIT read as zero, but are ignored on comparison. The result is that the limit is effectively FFFFFh. Add one MiB to the register value to make TSEG 8MiB instead of 7MiB. Fixes a crash related to SMRR not matching the TSEG region. Change-Id: I1a625f7bb53a3e90d3cbc0ce16021892861367d8 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/30932 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Werner Zeh --- src/soc/intel/fsp_broadwell_de/smmrelocate.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c index f8f98c231d..a58744e774 100644 --- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c +++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c @@ -220,9 +220,13 @@ static void fill_in_relocation_params(pci_devfn_t dev, * encompasses the SMRAM range as well as the IED range. * However, the SMRAM available to the handler is 4MiB since the IEDRAM * lives TSEG_BASE + 4MiB. + * + * Note that address bits 19:0 are ignored and not compared. + * The result is that BASE[19:0] is effectively 00000h and LIMIT is + * effectively FFFFFh. */ tseg_base = northbridge_get_base_reg(dev, TSEG_BASE); - tseg_limit = northbridge_get_base_reg(dev, TSEG_LIMIT); + tseg_limit = northbridge_get_base_reg(dev, TSEG_LIMIT) + 1 * MiB; tseg_size = tseg_limit - tseg_base; params->smram_base = tseg_base; -- cgit v1.2.3