From 74b85f2e2ec05eff9c08e6a6561210b0b00f8633 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 25 Jan 2022 12:16:44 -0600 Subject: soc/intel/cannonlake: Add PcieRpHotPlug config to FSP-M MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit b67c5ed [3rdparty/fsp: Update submodule pointer to newest master] updated the FSP binaries/headers for Comet Lake, which included a change moving PcieRpHotPlug from FSP-S to FSP-M. Unfortunately the existing UDP in FSP-S was left in and deprecated, which allowed the change to go unnoticed until it was discovered that hotplug wasn't working. Since other related platforms (WHL, CFL) share the SoC code but use different FSP packages, add the setting of the PcieRpHotPlug UPD to romstage/FSP-M and guard it with '#if CONFIG(SOC_INTEL_COMETLAKE)'. Test: build/boot Purism Librem 14, verify WiFi killswitch operates as expected / WiFi is re-enabled when turning switch to on position. Change-Id: I4e1c2ea909933ab21921e63ddeb31cefe1ceef13 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/61377 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/soc/intel/cannonlake/romstage/fsp_params.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 8cb6c92a65..0b63bd52f9 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -59,6 +59,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) m_cfg->EnableC6Dram = config->enable_c6dram; #if CONFIG(SOC_INTEL_COMETLAKE) m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + memcpy(tconfig->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(tconfig->PcieRpHotPlug)); #else m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; #endif -- cgit v1.2.3