From 703658a7ce1e6d1b5536a96251e4d1e708de4ac6 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 11 Jun 2019 09:43:05 +0200 Subject: soc/intel/fsp_broadwell_de: Implement SystemAgent TSEG functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement sa_get_tseg_base and sa_get_tseg_size. Used by Intel TXT and the new SMM API. Tested on OCP/Wedge100S. Change-Id: I22123cbf8d65b25a77fbf72ae8411b23b10c13b4 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/33418 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- .../fsp_broadwell_de/include/soc/broadwell_de.h | 3 +++ src/soc/intel/fsp_broadwell_de/memmap.c | 30 ++++++++++++++++++++++ 2 files changed, 33 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h index edfeafc8a4..4167895729 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h @@ -18,6 +18,9 @@ #ifndef _SOC_BROADWELL_DE_H_ #define _SOC_BROADWELL_DE_H_ +uintptr_t sa_get_tseg_base(void); +size_t sa_get_tseg_size(void); + #define VTBAR_OFFSET 0x180 #define VTBAR_MASK 0xffffe000 #define VTBAR_ENABLED 0x01 diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c index 75100948b9..36f400c7b3 100644 --- a/src/soc/intel/fsp_broadwell_de/memmap.c +++ b/src/soc/intel/fsp_broadwell_de/memmap.c @@ -14,10 +14,40 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include #include +#include +#include +#include void *cbmem_top(void) { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } + +/* + * Get TSEG base. + */ +uintptr_t sa_get_tseg_base(void) +{ + const pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC); + + /* All regions concerned for have 1 MiB alignment. */ + return ALIGN_DOWN(pci_read_config32(dev, TSEG_BASE), 1 * MiB); +} + +size_t sa_get_tseg_size(void) +{ + const pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC); + + /* All regions concerned for have 1 MiB alignment. */ + size_t ret = ALIGN_DOWN(pci_read_config32(dev, TSEG_LIMIT), 1 * MiB); + + /* Lower 20bit of TSEG_LIMIT are don't care, need to add 1MiB */ + ret += 1 * MiB; + + /* Subtract base to get the size */ + return ret - sa_get_tseg_base(); +} -- cgit v1.2.3