From 662c61d4497544d10c6b0d103ec7c27b5b084ee6 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 16 Aug 2019 11:56:40 +0530 Subject: soc/intel/cnl: Add provision to configure SD controller write protect pin Cometlake FSP allows provison to configure SD controller WP pin, As some of board design might choose not to use the SD WP pin from SD card controller. This implementation adds a config that allows to enable/disable SD controller WP pin configuration from FSP. BUG=b:123907904 Change-Id: Ic1736a2ec4b9370d23a8e3349603eb363e6f59b9 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/34900 Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Fagerburg Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/chip.h | 2 ++ src/soc/intel/cannonlake/fsp_params.c | 3 +++ 2 files changed, 5 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 71aa2086d5..fa98cd41a7 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -186,6 +186,8 @@ struct soc_intel_cannonlake_config { uint8_t EmmcHs400RxStrobeDll1; /* 0-78: number of active delay for TX data, unit is 125 psec */ uint8_t EmmcHs400TxDataDll; + /* Enable/disable SD card write protect pin configuration on CML */ + uint8_t ScsSdCardWpPinEnabled; /* Integrated Sensor */ uint8_t PchIshEnable; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 0f27c47bac..494c1db3fb 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -336,6 +336,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->ScsSdCardEnabled = dev->enabled; params->SdCardPowerEnableActiveHigh = CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); +#if CONFIG(SOC_INTEL_COMETLAKE) + params->ScsSdCardWpPinEnabled = config->ScsSdCardWpPinEnabled; +#endif } dev = pcidev_path_on_root(PCH_DEVFN_UFS); -- cgit v1.2.3