From 59b6542bbc5aa7215aa68eca098c047924e5e118 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 23 May 2019 15:24:30 +0200 Subject: soc/intel/braswell: Use common cpu/intel/car code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code in cpu/intel/car/romstage.c Does most of the things like setting up timestamps, stack guards, entering postcar. A functional difference is that the FSP header is searched for twice instead of passed from the CAR entry to the C code. When using C_ENVIRONMENT_BOOTBLOCK this needs to be done anyway (or a special linker symbol kept across multiple stages is needed, which is likely not worth the speedup). Change-Id: I0f03e5a808f00157fdd807b104417a54e4bde7b2 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32963 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/braswell/romstage/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index 15de822041..3d3e407a29 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,2 +1,3 @@ +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += pmc.c romstage-y += romstage.c -- cgit v1.2.3