From 588c2c42c3609785e3856f76bab884ff563b40ca Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 14 Aug 2017 16:30:59 +0530 Subject: soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definition LPC pci config register BIOS Control (BC) - offset 0xDC bit 1 is for Lock Down. Change-Id: I4780d2e41c833c0146640f715759dbb0a948c4ab Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/21001 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/include/soc/lpc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h index 3488ee2b85..3ea9be9203 100644 --- a/src/soc/intel/cannonlake/include/soc/lpc.h +++ b/src/soc/intel/cannonlake/include/soc/lpc.h @@ -48,7 +48,7 @@ #define LGMR 0x98 /* LPC Generic Memory Range */ #define BIOS_CNTL 0xdc #define LPC_BC_BILD (1 << 7) /* BILD */ -#define LPC_BC_LE (1 << 2) /* LE */ +#define LPC_BC_LE (1 << 1) /* LE */ #define LPC_BC_EISS (1 << 5) /* EISS */ #define PCCTL 0xE0 /* PCI Clock Control */ #define CLKRUN_EN (1 << 0) -- cgit v1.2.3