From 566feddeceb421ba6480bcee94f87bc4c95c6196 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 28 Oct 2016 14:55:46 -0700 Subject: soc/intel/common: Add reset.c to postcar ramstage_cache_invalid which was added in I83fe76957c061f20e9afb308e55923806fda4f93 (review.coreboot.org/#/c/17112) requires hard_reset to be defined in postcar stage. BUG=None BRANCH=None TEST=Compiles successfully for reef. Change-Id: I283277c373259e0e2dfe72e3c889ceea012544f2 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/17182 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/common/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 888c657f3e..38903a0ae7 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -15,6 +15,7 @@ romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c postcar-y += util.c +postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c -- cgit v1.2.3