From 540a98001d05a7b780e415c34d14a97b14e44ac6 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 9 Dec 2019 13:03:29 -0800 Subject: printf: Automatically prefix %p with 0x According to the POSIX standard, %p is supposed to print a pointer "as if by %#x", meaning the "0x" prefix should automatically be prepended. All other implementations out there (glibc, Linux, even libpayload) do this, so we should make coreboot match. This patch changes vtxprintf() accordingly and removes any explicit instances of "0x%p" from existing format strings. How to handle zero padding is less clear: the official POSIX definition above technically says there should be no automatic zero padding, but in practice most other implementations seem to do it and I assume most programmers would prefer it. The way chosen here is to always zero-pad to 32 bits, even on a 64-bit system. The rationale for this is that even on 64-bit systems, coreboot always avoids using any memory above 4GB for itself, so in practice all pointers should fit in that range and padding everything to 64 bits would just hurt readability. Padding it this way also helps pointers that do exceed 4GB (e.g. prints from MMU config on some arm64 systems) stand out better from the others. Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi Reviewed-by: David Guckian --- src/soc/intel/braswell/southcluster.c | 2 +- src/soc/intel/common/mma.c | 2 +- src/soc/intel/denverton_ns/hob_mem.c | 2 +- src/soc/intel/quark/bootblock/bootblock.c | 2 +- src/soc/intel/quark/i2c.c | 2 +- src/soc/intel/quark/romstage/debug.c | 2 +- src/soc/intel/quark/romstage/fsp_params.c | 6 +++--- 7 files changed, 9 insertions(+), 9 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 8b13fd0e82..b2d13d5642 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -618,7 +618,7 @@ static void finalize_chipset(void *unused) uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; struct vscc_config cfg; - printk(BIOS_SPEW, "%s/%s (0x%p)\n", + printk(BIOS_SPEW, "%s/%s (%p)\n", __FILE__, __func__, unused); /* Set the lock enable on the BIOS control register. */ diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c index 1b3a82a088..2cd35ea6cd 100644 --- a/src/soc/intel/common/mma.c +++ b/src/soc/intel/common/mma.c @@ -219,7 +219,7 @@ static void save_mma_results_data(void *unused) memset(mma_data, 0, mma_data_size); printk(BIOS_DEBUG, - "MMA: copy MMA data to CBMEM(src 0x%p, dest 0x%p, %u bytes)\n", + "MMA: copy MMA data to CBMEM(src %p, dest %p, %u bytes)\n", mma_hob, mma_data, mma_hob_size); mma_data->mma_signature = MMA_DATA_SIGNATURE; diff --git a/src/soc/intel/denverton_ns/hob_mem.c b/src/soc/intel/denverton_ns/hob_mem.c index e4aa78f291..a00a4f498c 100644 --- a/src/soc/intel/denverton_ns/hob_mem.c +++ b/src/soc/intel/denverton_ns/hob_mem.c @@ -52,7 +52,7 @@ void soc_save_dimm_info(void) * table 17 */ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info); if (mem_info == NULL) return; memset(mem_info, 0, sizeof(*mem_info)); diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 2b2fc29f59..957b4a0c37 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -118,6 +118,6 @@ void bootblock_soc_init(void) void platform_prog_run(struct prog *prog) { /* Display the program entry point */ - printk(BIOS_SPEW, "Calling %s, 0x%p(0x%p)\n", prog->name, + printk(BIOS_SPEW, "Calling %s, %p(%p)\n", prog->name, prog->entry, prog->arg); } diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index b09852bc3f..7ff2ddf93f 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -209,7 +209,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment, if (index == 0) printk(BIOS_ERR, "I2C Start\n"); printk(BIOS_ERR, - "I2C segment[%d]: %s 0x%02x %s 0x%p, 0x%08x bytes\n", + "I2C segment[%d]: %s 0x%02x %s %p, 0x%08x bytes\n", index, (segment[index].flags & I2C_M_RD) ? "Read from" : "Write to", segment[index].slave, diff --git a/src/soc/intel/quark/romstage/debug.c b/src/soc/intel/quark/romstage/debug.c index 1029eadb93..e0cf6c8262 100644 --- a/src/soc/intel/quark/romstage/debug.c +++ b/src/soc/intel/quark/romstage/debug.c @@ -26,7 +26,7 @@ void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd, new = &fspm_new_upd->FspmConfig; /* Display the parameters for MemoryInit */ - printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); + printk(BIOS_SPEW, "UPD values for MemoryInit at: %p\n", new); fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), old->AddrMode, new->AddrMode); fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), diff --git a/src/soc/intel/quark/romstage/fsp_params.c b/src/soc/intel/quark/romstage/fsp_params.c index 681e126a13..c31cafb14f 100644 --- a/src/soc/intel/quark/romstage/fsp_params.c +++ b/src/soc/intel/quark/romstage/fsp_params.c @@ -111,13 +111,13 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) "+-------------------+ 0x%08x (CONFIG_FSP_ESRAM_LOC)\n", CONFIG_FSP_ESRAM_LOC); printk(BIOS_SPEW, "| FSP stack |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + printk(BIOS_SPEW, "+-------------------+ %p\n", aupd->StackBase); printk(BIOS_SPEW, "| |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + printk(BIOS_SPEW, "+-------------------+ %p\n", _car_unallocated_start); printk(BIOS_SPEW, "| coreboot data |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + printk(BIOS_SPEW, "+-------------------+ %p\n", _ecar_stack); printk(BIOS_SPEW, "| coreboot stack |\n"); printk(BIOS_SPEW, -- cgit v1.2.3